1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2010 Adrian Chadd
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /* $FreeBSD$ */
30
31 #ifndef __AR71XX_CPUDEF_H__
32 #define __AR71XX_CPUDEF_H__
33
34 typedef enum {
35 AR71XX_CPU_DDR_FLUSH_GE0,
36 AR71XX_CPU_DDR_FLUSH_GE1,
37 AR71XX_CPU_DDR_FLUSH_USB,
38 AR71XX_CPU_DDR_FLUSH_PCIE,
39 AR71XX_CPU_DDR_FLUSH_WMAC,
40 AR71XX_CPU_DDR_FLUSH_PCIE_EP,
41 AR71XX_CPU_DDR_FLUSH_CHECKSUM,
42 } ar71xx_flush_ddr_id_t;
43
44 struct ar71xx_cpu_def {
45 void (* detect_mem_size) (void);
46 void (* detect_sys_frequency) (void);
47 void (* ar71xx_chip_device_stop) (uint32_t);
48 void (* ar71xx_chip_device_start) (uint32_t);
49 int (* ar71xx_chip_device_stopped) (uint32_t);
50 void (* ar71xx_chip_set_pll_ge) (int, int, uint32_t);
51 void (* ar71xx_chip_set_mii_speed) (uint32_t, uint32_t);
52 void (* ar71xx_chip_set_mii_if) (uint32_t, ar71xx_mii_mode);
53 uint32_t (* ar71xx_chip_get_eth_pll) (unsigned int, int);
54
55 /*
56 * From Linux - Handling this IRQ is a bit special.
57 * AR71xx - AR71XX_DDR_REG_FLUSH_PCI
58 * AR724x - AR724X_DDR_REG_FLUSH_PCIE
59 * AR91xx - AR91XX_DDR_REG_FLUSH_WMAC
60 *
61 * These are set when STATUSF_IP2 is set in regiser c0.
62 * This flush is done before the IRQ is handled to make
63 * sure the driver correctly sees any memory updates.
64 */
65 void (* ar71xx_chip_ddr_flush) (ar71xx_flush_ddr_id_t id);
66 /*
67 * The USB peripheral init code is subtly different for
68 * each chip.
69 */
70 void (* ar71xx_chip_init_usb_peripheral) (void);
71
72 void (* ar71xx_chip_reset_ethernet_switch) (void);
73
74 void (* ar71xx_chip_reset_wmac) (void);
75
76 void (* ar71xx_chip_init_gmac) (void);
77
78 void (* ar71xx_chip_reset_nfc) (int);
79
80 void (* ar71xx_chip_gpio_out_configure) (int, uint8_t);
81 };
82
83 extern struct ar71xx_cpu_def * ar71xx_cpu_ops;
84
ar71xx_detect_sys_frequency(void)85 static inline void ar71xx_detect_sys_frequency(void)
86 {
87 ar71xx_cpu_ops->detect_sys_frequency();
88 }
89
ar71xx_device_stop(uint32_t mask)90 static inline void ar71xx_device_stop(uint32_t mask)
91 {
92 ar71xx_cpu_ops->ar71xx_chip_device_stop(mask);
93 }
94
ar71xx_device_start(uint32_t mask)95 static inline void ar71xx_device_start(uint32_t mask)
96 {
97 ar71xx_cpu_ops->ar71xx_chip_device_start(mask);
98 }
99
ar71xx_device_stopped(uint32_t mask)100 static inline int ar71xx_device_stopped(uint32_t mask)
101 {
102 return ar71xx_cpu_ops->ar71xx_chip_device_stopped(mask);
103 }
104
ar71xx_device_set_pll_ge(int unit,int speed,uint32_t pll)105 static inline void ar71xx_device_set_pll_ge(int unit, int speed, uint32_t pll)
106 {
107 ar71xx_cpu_ops->ar71xx_chip_set_pll_ge(unit, speed, pll);
108 }
109
ar71xx_device_set_mii_speed(int unit,int speed)110 static inline void ar71xx_device_set_mii_speed(int unit, int speed)
111 {
112 ar71xx_cpu_ops->ar71xx_chip_set_mii_speed(unit, speed);
113 }
114
ar71xx_device_set_mii_if(int unit,ar71xx_mii_mode mii_cfg)115 static inline void ar71xx_device_set_mii_if(int unit, ar71xx_mii_mode mii_cfg)
116 {
117 ar71xx_cpu_ops->ar71xx_chip_set_mii_if(unit, mii_cfg);
118 }
119
ar71xx_device_flush_ddr(ar71xx_flush_ddr_id_t id)120 static inline void ar71xx_device_flush_ddr(ar71xx_flush_ddr_id_t id)
121 {
122 ar71xx_cpu_ops->ar71xx_chip_ddr_flush(id);
123 }
124
ar71xx_device_get_eth_pll(unsigned int unit,int speed)125 static inline uint32_t ar71xx_device_get_eth_pll(unsigned int unit, int speed)
126 {
127 return (ar71xx_cpu_ops->ar71xx_chip_get_eth_pll(unit, speed));
128 }
129
ar71xx_init_usb_peripheral(void)130 static inline void ar71xx_init_usb_peripheral(void)
131 {
132 ar71xx_cpu_ops->ar71xx_chip_init_usb_peripheral();
133 }
134
ar71xx_reset_ethernet_switch(void)135 static inline void ar71xx_reset_ethernet_switch(void)
136 {
137 if (ar71xx_cpu_ops->ar71xx_chip_reset_ethernet_switch)
138 ar71xx_cpu_ops->ar71xx_chip_reset_ethernet_switch();
139 }
140
ar71xx_reset_wmac(void)141 static inline void ar71xx_reset_wmac(void)
142 {
143 if (ar71xx_cpu_ops->ar71xx_chip_reset_wmac)
144 ar71xx_cpu_ops->ar71xx_chip_reset_wmac();
145 }
146
ar71xx_init_gmac(void)147 static inline void ar71xx_init_gmac(void)
148 {
149 if (ar71xx_cpu_ops->ar71xx_chip_init_gmac)
150 ar71xx_cpu_ops->ar71xx_chip_init_gmac();
151 }
152
ar71xx_reset_nfc(int active)153 static inline void ar71xx_reset_nfc(int active)
154 {
155
156 if (ar71xx_cpu_ops->ar71xx_chip_reset_nfc)
157 ar71xx_cpu_ops->ar71xx_chip_reset_nfc(active);
158 }
159
ar71xx_gpio_ouput_configure(int gpio,uint8_t func)160 static inline void ar71xx_gpio_ouput_configure(int gpio, uint8_t func)
161 {
162 if (ar71xx_cpu_ops->ar71xx_chip_gpio_out_configure)
163 ar71xx_cpu_ops->ar71xx_chip_gpio_out_configure(gpio, func);
164 }
165
166 /* XXX shouldn't be here! */
167 extern uint32_t u_ar71xx_refclk;
168 extern uint32_t u_ar71xx_cpu_freq;
169 extern uint32_t u_ar71xx_ahb_freq;
170 extern uint32_t u_ar71xx_ddr_freq;
171 extern uint32_t u_ar71xx_uart_freq;
172 extern uint32_t u_ar71xx_wdt_freq;
173 extern uint32_t u_ar71xx_mdio_freq;
ar71xx_refclk(void)174 static inline uint64_t ar71xx_refclk(void) { return u_ar71xx_refclk; }
ar71xx_cpu_freq(void)175 static inline uint64_t ar71xx_cpu_freq(void) { return u_ar71xx_cpu_freq; }
ar71xx_ahb_freq(void)176 static inline uint64_t ar71xx_ahb_freq(void) { return u_ar71xx_ahb_freq; }
ar71xx_ddr_freq(void)177 static inline uint64_t ar71xx_ddr_freq(void) { return u_ar71xx_ddr_freq; }
ar71xx_uart_freq(void)178 static inline uint64_t ar71xx_uart_freq(void) { return u_ar71xx_uart_freq; }
ar71xx_wdt_freq(void)179 static inline uint64_t ar71xx_wdt_freq(void) { return u_ar71xx_wdt_freq; }
ar71xx_mdio_freq(void)180 static inline uint64_t ar71xx_mdio_freq(void) { return u_ar71xx_mdio_freq; }
181
182 #endif
183