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/f-stack/freebsd/arm/freescale/vybrid/
H A Dvf_common.h31 #define READ4(_sc, _reg) \ argument
32 bus_space_read_4(_sc->bst, _sc->bsh, _reg)
33 #define WRITE4(_sc, _reg, _val) \ argument
34 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
35 #define READ2(_sc, _reg) \ argument
36 bus_space_read_2(_sc->bst, _sc->bsh, _reg)
37 #define WRITE2(_sc, _reg, _val) \ argument
38 bus_space_write_2(_sc->bst, _sc->bsh, _reg, _val)
39 #define READ1(_sc, _reg) \ argument
40 bus_space_read_1(_sc->bst, _sc->bsh, _reg)
[all …]
H A Dvf_edma.h113 #define TCD_READ4(_sc, _reg) \ argument
114 bus_space_read_4(_sc->bst_tcd, _sc->bsh_tcd, _reg)
115 #define TCD_WRITE4(_sc, _reg, _val) \ argument
116 bus_space_write_4(_sc->bst_tcd, _sc->bsh_tcd, _reg, _val)
117 #define TCD_READ2(_sc, _reg) \ argument
118 bus_space_read_2(_sc->bst_tcd, _sc->bsh_tcd, _reg)
119 #define TCD_WRITE2(_sc, _reg, _val) \ argument
120 bus_space_write_2(_sc->bst_tcd, _sc->bsh_tcd, _reg, _val)
121 #define TCD_READ1(_sc, _reg) \ argument
122 bus_space_read_1(_sc->bst_tcd, _sc->bsh_tcd, _reg)
[all …]
H A Dvf_dmamux.h46 #define MUX_READ1(_sc, _mux, _reg) \ argument
47 bus_space_read_1(_sc->bst[_mux], _sc->bsh[_mux], _reg)
49 #define MUX_WRITE1(_sc, _mux, _reg, _val) \ argument
50 bus_space_write_1(_sc->bst[_mux], _sc->bsh[_mux], _reg, _val)
/f-stack/freebsd/arm/ti/
H A Dti_adcvar.h34 #define ADC_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg) argument
35 #define ADC_WRITE4(_sc, reg, value) \ argument
75 #define TI_ADC_LOCK(_sc) \ argument
76 mtx_lock(&(_sc)->sc_mtx)
77 #define TI_ADC_UNLOCK(_sc) \ argument
78 mtx_unlock(&(_sc)->sc_mtx)
79 #define TI_ADC_LOCK_INIT(_sc) \ argument
80 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
82 #define TI_ADC_LOCK_DESTROY(_sc) \ argument
83 mtx_destroy(&_sc->sc_mtx);
[all …]
H A Dti_spivar.h61 #define TI_SPI_WRITE(_sc, _off, _val) \ argument
62 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off), (_val))
63 #define TI_SPI_READ(_sc, _off) \ argument
64 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off))
66 #define TI_SPI_LOCK(_sc) \ argument
67 mtx_lock(&(_sc)->sc_mtx)
68 #define TI_SPI_UNLOCK(_sc) \ argument
69 mtx_unlock(&(_sc)->sc_mtx)
/f-stack/freebsd/arm/altera/socfpga/
H A Dsocfpga_common.h33 #define READ4(_sc, _reg) bus_read_4((_sc)->res[0], _reg) argument
34 #define READ2(_sc, _reg) bus_read_2((_sc)->res[0], _reg) argument
35 #define READ1(_sc, _reg) bus_read_1((_sc)->res[0], _reg) argument
36 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) argument
37 #define WRITE2(_sc, _reg, _val) bus_write_2((_sc)->res[0], _reg, _val) argument
38 #define WRITE1(_sc, _reg, _val) bus_write_1((_sc)->res[0], _reg, _val) argument
/f-stack/freebsd/mips/mediatek/
H A Dmtk_usb_phy.c60 #define USB_PHY_READ(_sc, _off) bus_read_4((_sc)->res, (_off)) argument
61 #define USB_PHY_WRITE(_sc, _off, _val) bus_write_4((_sc)->res, (_off), (_val)) argument
63 USB_PHY_WRITE(_sc, _off, ((USB_PHY_READ(_sc, _off) & ~(_clr)) | (_set)))
65 #define USB_PHY_READ_U2(_sc, _off) \ argument
66 USB_PHY_READ((_sc), ((_sc)->u2_base + (_off)))
68 USB_PHY_WRITE((_sc), ((_sc)->u2_base + (_off)), (_val))
70 USB_PHY_WRITE_U2((_sc), (_off), ((USB_PHY_READ_U2((_sc), (_off)) & \
72 #define USB_PHY_BARRIER(_sc) bus_barrier((_sc)->res, 0, 0, \ argument
76 USB_PHY_READ((_sc), ((_sc)->fm_base + (_off)))
78 USB_PHY_WRITE((_sc), ((_sc)->fm_base + (_off)), (_val))
[all …]
/f-stack/freebsd/arm/ti/am335x/
H A Dam335x_ecap.c60 #define ECAP_READ2(_sc, reg) bus_read_2((_sc)->sc_mem_res, reg); argument
61 #define ECAP_WRITE2(_sc, reg, value) \ argument
62 bus_write_2((_sc)->sc_mem_res, reg, value);
63 #define ECAP_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg); argument
64 #define ECAP_WRITE4(_sc, reg, value) \ argument
65 bus_write_4((_sc)->sc_mem_res, reg, value);
67 #define PWM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
68 #define PWM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
69 #define PWM_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \ argument
70 device_get_nameunit(_sc->sc_dev), "am335x_ecap softc", MTX_DEF)
[all …]
H A Dam335x_rtc.c48 #define RTC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
49 #define RTC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
50 #define RTC_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \ argument
51 device_get_nameunit(_sc->sc_dev), "am335x_rtc", MTX_DEF)
52 #define RTC_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) argument
54 #define RTC_READ4(_sc, reg) \ argument
55 bus_read_4((_sc)->sc_mem_res, reg)
56 #define RTC_WRITE4(_sc, reg, value) \ argument
57 bus_write_4((_sc)->sc_mem_res, reg, value)
/f-stack/freebsd/arm/broadcom/bcm2835/
H A Dbcm2835_spivar.h52 #define BCM_SPI_WRITE(_sc, _off, _val) \ argument
53 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val)
54 #define BCM_SPI_READ(_sc, _off) \ argument
55 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off)
57 #define BCM_SPI_LOCK(_sc) \ argument
58 mtx_lock(&(_sc)->sc_mtx)
59 #define BCM_SPI_UNLOCK(_sc) \ argument
60 mtx_unlock(&(_sc)->sc_mtx)
H A Dbcm2835_pwm.c78 bus_space_read_4(_sc->sc_m_bst, _sc->sc_m_bsh, _off)
82 bus_space_read_4(_sc->sc_c_bst, _sc->sc_c_bsh, _off)
84 #define W_CTL(_sc, _val) BCM_PWM_MEM_WRITE(_sc, 0x00, _val) argument
85 #define R_CTL(_sc) BCM_PWM_MEM_READ(_sc, 0x00) argument
86 #define W_STA(_sc, _val) BCM_PWM_MEM_WRITE(_sc, 0x04, _val) argument
87 #define R_STA(_sc) BCM_PWM_MEM_READ(_sc, 0x04) argument
88 #define W_RNG(_sc, _val) BCM_PWM_MEM_WRITE(_sc, 0x10, _val) argument
89 #define R_RNG(_sc) BCM_PWM_MEM_READ(_sc, 0x10) argument
91 #define R_DAT(_sc) BCM_PWM_MEM_READ(_sc, 0x14) argument
93 #define R_RNG2(_sc) BCM_PWM_MEM_READ(_sc, 0x20) argument
[all …]
H A Dbcm2835_bscvar.h61 #define BCM_BSC_WRITE(_sc, _off, _val) \ argument
62 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _off, _val)
63 #define BCM_BSC_READ(_sc, _off) \ argument
64 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _off)
66 #define BCM_BSC_LOCK(_sc) \ argument
67 mtx_lock(&(_sc)->sc_mtx)
68 #define BCM_BSC_UNLOCK(_sc) \ argument
69 mtx_unlock(&(_sc)->sc_mtx)
H A Dbcm2835_clkman.c67 #define BCM_CLKMAN_WRITE(_sc, _off, _val) \ argument
68 bus_space_write_4(_sc->sc_m_bst, _sc->sc_m_bsh, _off, _val)
69 #define BCM_CLKMAN_READ(_sc, _off) \ argument
70 bus_space_read_4(_sc->sc_m_bst, _sc->sc_m_bsh, _off)
72 #define W_CMCLK(_sc, unit, _val) BCM_CLKMAN_WRITE(_sc, unit, 0x5a000000 | (_val)) argument
73 #define R_CMCLK(_sc, unit) BCM_CLKMAN_READ(_sc, unit) argument
74 #define W_CMDIV(_sc, unit, _val) BCM_CLKMAN_WRITE(_sc, (unit) + 4, 0x5a000000 | (_val)) argument
75 #define R_CMDIV(_sc, unit) BCM_CLKMAN_READ(_sc, (unit) + 4) argument
/f-stack/freebsd/mips/atheros/
H A Dif_argevar.h55 #define ARGE_LOCK(_sc) mtx_lock(&(_sc)->arge_mtx) argument
56 #define ARGE_UNLOCK(_sc) mtx_unlock(&(_sc)->arge_mtx) argument
57 #define ARGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->arge_mtx, MA_OWNED) argument
91 #define ARGE_MDIO_WRITE(_sc, _reg, _val) \ argument
92 ARGE_WRITE((_sc), (_reg), (_val))
93 #define ARGE_MDIO_READ(_sc, _reg) \ argument
94 ARGE_READ((_sc), (_reg))
95 #define ARGE_MDIO_BARRIER_READ(_sc) ARGE_BARRIER_READ(_sc) argument
96 #define ARGE_MDIO_BARRIER_WRITE(_sc) ARGE_BARRIER_WRITE(_sc) argument
97 #define ARGE_MDIO_BARRIER_RW(_sc) ARGE_BARRIER_RW(_sc) argument
H A Dar71xx_gpiovar.h37 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->gpio_mtx) argument
38 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->gpio_mtx) argument
39 #define GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->gpio_mtx, MA_OWNED) argument
/f-stack/freebsd/mips/nlm/dev/net/
H A Dxlpge.h133 #define XLPGE_LOCK_INIT(_sc, _name) \ argument
134 mtx_init(&(_sc)->sc_lock, _name, MTX_NETWORK_LOCK, MTX_DEF)
135 #define XLPGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_lock) argument
136 #define XLPGE_LOCK(_sc) mtx_lock(&(_sc)->sc_lock) argument
137 #define XLPGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_lock) argument
138 #define XLPGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_lock, MA_OWNED) argument
/f-stack/freebsd/arm/nvidia/
H A Dtegra_mc.c99 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) argument
100 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) argument
102 #define LOCK(_sc) mtx_lock(&(_sc)->mtx) argument
103 #define UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) argument
104 #define SLEEP(_sc, timeout) mtx_sleep(sc, &sc->mtx, 0, "tegra_mc", timeout); argument
105 #define LOCK_INIT(_sc) \ argument
106 mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "tegra_mc", MTX_DEF)
107 #define LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx) argument
108 #define ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED) argument
109 #define ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED) argument
H A Dtegra_rtc.c77 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) argument
78 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) argument
80 #define LOCK(_sc) mtx_lock(&(_sc)->mtx) argument
81 #define UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) argument
82 #define SLEEP(_sc, timeout) \ argument
84 #define LOCK_INIT(_sc) \ argument
85 mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "tegra_rtc", MTX_DEF)
86 #define LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx) argument
87 #define ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED) argument
88 #define ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED) argument
/f-stack/freebsd/mips/ingenic/
H A Djz4780_common.h33 #define READ4(_sc, _reg) \ argument
34 bus_space_read_4(_sc->bst, _sc->bsh, _reg)
35 #define WRITE4(_sc, _reg, _val) \ argument
36 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
H A Djz4780_clk.h43 #define CLK_LOCK(_sc) mtx_lock((_sc)->clk_mtx) argument
44 #define CLK_UNLOCK(_sc) mtx_unlock((_sc)->clk_mtx) argument
46 #define CLK_WR_4(_sc, off, val) bus_write_4((_sc)->clk_res, (off), (val)) argument
47 #define CLK_RD_4(_sc, off) bus_read_4((_sc)->clk_res, (off)) argument
/f-stack/freebsd/mips/cavium/
H A Docteon_gpiovar.h36 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->gpio_mtx) argument
37 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->gpio_mtx) argument
38 #define GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->gpio_mtx, MA_OWNED) argument
/f-stack/freebsd/mips/atheros/ar531x/
H A Dar5315_gpiovar.h37 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->gpio_mtx) argument
38 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->gpio_mtx) argument
39 #define GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->gpio_mtx, MA_OWNED) argument
/f-stack/freebsd/arm/ti/twl/
H A Dtwl_clks.c137 #define TWL_CLKS_XLOCK(_sc) sx_xlock(&(_sc)->sc_sx) argument
138 #define TWL_CLKS_XUNLOCK(_sc) sx_xunlock(&(_sc)->sc_sx) argument
139 #define TWL_CLKS_SLOCK(_sc) sx_slock(&(_sc)->sc_sx) argument
140 #define TWL_CLKS_SUNLOCK(_sc) sx_sunlock(&(_sc)->sc_sx) argument
141 #define TWL_CLKS_LOCK_INIT(_sc) sx_init(&(_sc)->sc_sx, "twl_clks") argument
142 #define TWL_CLKS_LOCK_DESTROY(_sc) sx_destroy(&(_sc)->sc_sx); argument
144 #define TWL_CLKS_ASSERT_LOCKED(_sc) sx_assert(&(_sc)->sc_sx, SA_LOCKED); argument
146 #define TWL_CLKS_LOCK_UPGRADE(_sc) \ argument
148 while (!sx_try_upgrade(&(_sc)->sc_sx)) \
151 #define TWL_CLKS_LOCK_DOWNGRADE(_sc) sx_downgrade(&(_sc)->sc_sx); argument
H A Dtwl.c114 #define TWL_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
115 #define TWL_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
116 #define TWL_LOCK_INIT(_sc) \ argument
117 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
119 #define TWL_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); argument
120 #define TWL_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); argument
121 #define TWL_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); argument
/f-stack/freebsd/arm/nvidia/tegra124/
H A Dtegra124_pmc.c137 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) argument
138 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) argument
140 #define PMC_LOCK(_sc) mtx_lock(&(_sc)->mtx) argument
141 #define PMC_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) argument
142 #define PMC_LOCK_INIT(_sc) mtx_init(&(_sc)->mtx, \ argument
143 device_get_nameunit(_sc->dev), "tegra124_pmc", MTX_DEF)
144 #define PMC_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx); argument
145 #define PMC_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED); argument
146 #define PMC_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED); argument

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