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/f-stack/dpdk/lib/librte_eal/windows/include/
H A Dsched.h38 for (_i = 0; _i < _NUM_SETS(CPU_SETSIZE); _i++) \
48 unsigned int _i; in count_cpu() local
51 for (_i = 0; _i < _NUM_SETS(CPU_SETSIZE); _i++) in count_cpu()
60 unsigned int _i; \
62 for (_i = 0; _i < _NUM_SETS(CPU_SETSIZE); _i++) \
63 (dst)->_bits[_i] = (src1)->_bits[_i] & (src2)->_bits[_i]; \
70 for (_i = 0; _i < _NUM_SETS(CPU_SETSIZE); _i++) \
71 (dst)->_bits[_i] = (src1)->_bits[_i] | (src2)->_bits[_i]; \
77 for (_i = 0; _i < _NUM_SETS(CPU_SETSIZE); _i++) \
84 for (_i = 0; _i < _NUM_SETS(CPU_SETSIZE); _i++) \
[all …]
/f-stack/dpdk/drivers/net/ice/base/
H A Dice_hw_autogen.h26 #define MSIX_PBA(_i) (0x00008000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: FLR */ argument
30 #define MSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */ argument
36 #define MSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */ argument
40 #define MSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */ argument
769 #define GL_SWT_L2TAG0(_i) (0x000492A8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ argument
773 #define GL_SWT_L2TAG1(_i) (0x000492C8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ argument
5625 #define MSIX_PBA1(_i) (0x00008000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: FLR */ argument
7116 #define GLRPB_SHW(_i) (0x000AC120 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ argument
7120 #define GLRPB_SLW(_i) (0x000AC140 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ argument
9014 #define PRTPM_SAH(_i) (0x001E3BA0 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: PFR */ argument
[all …]
H A Dice_nvm.h60 #define GL_HIDA(_i) (0x00082000 + ((_i) * 4)) argument
61 #define GL_HIBA(_i) (0x00081000 + ((_i) * 4)) argument
/f-stack/dpdk/drivers/net/i40e/base/
H A Di40e_register.h177 #define I40E_PFCM_LANCTXDATA(_i) (0x0010C100 + ((_i) * 128)) /* _i=0...3 */ /* Reset: CORER … argument
293 #define I40E_PRTDCB_RUPTQ(_i) (0x00122400 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ argument
300 #define I40E_PRTDCB_TCMSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ argument
311 #define I40E_PRTDCB_TCWSTC(_i) (0x000A2040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ argument
437 #define I40E_GLGEN_I2CCMD(_i) (0x000881E0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ argument
1469 #define I40E_PRT_MNG_MAVTV(_i) (0x00255900 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */ argument
1583 #define I40E_MSIX_PBA(_i) (0x00001000 + ((_i) * 4)) /* _i=0...5 */ /* Reset: FLR */ argument
2617 #define I40E_GLPRT_RFC(_i) (0x00300560 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ argument
2621 #define I40E_GLPRT_RJC(_i) (0x00300580 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ argument
2629 #define I40E_GLPRT_ROC(_i) (0x00300120 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ argument
[all …]
/f-stack/dpdk/drivers/crypto/nitrox/
H A Dnitrox_csr.h15 #define NPS_PKT_IN_INSTR_CTLX(_i) (0x10060UL + ((_i) * 0x40000UL)) argument
16 #define NPS_PKT_IN_INSTR_BADDRX(_i) (0x10068UL + ((_i) * 0x40000UL)) argument
17 #define NPS_PKT_IN_INSTR_RSIZEX(_i) (0x10070UL + ((_i) * 0x40000UL)) argument
18 #define NPS_PKT_IN_DONE_CNTSX(_i) (0x10080UL + ((_i) * 0x40000UL)) argument
19 #define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i) (0x10078UL + ((_i) * 0x40000UL)) argument
20 #define NPS_PKT_IN_INT_LEVELSX(_i) (0x10088UL + ((_i) * 0x40000UL)) argument
21 #define NPS_PKT_SLC_CTLX(_i) (0x10000UL + ((_i) * 0x40000UL)) argument
22 #define NPS_PKT_SLC_CNTSX(_i) (0x10008UL + ((_i) * 0x40000UL)) argument
23 #define NPS_PKT_SLC_INT_LEVELSX(_i) (0x10010UL + ((_i) * 0x40000UL)) argument
26 #define AQMQ_QSZX(_i) (0x20008UL + ((_i) * 0x40000UL)) argument
/f-stack/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_type.h336 #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \ argument
365 #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \ argument
367 #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \ argument
369 #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \ argument
371 #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \ argument
373 #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \ argument
389 #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \ argument
418 #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ argument
420 #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ argument
425 #define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \ argument
[all …]
H A Dixgbe_osdep.h69 #define IXGBE_NTOHL(_i) rte_be_to_cpu_32(_i) argument
70 #define IXGBE_NTOHS(_i) rte_be_to_cpu_16(_i) argument
71 #define IXGBE_CPU_TO_LE16(_i) rte_cpu_to_le_16(_i) argument
72 #define IXGBE_CPU_TO_LE32(_i) rte_cpu_to_le_32(_i) argument
73 #define IXGBE_LE32_TO_CPU(_i) rte_le_to_cpu_32(_i) argument
74 #define IXGBE_LE32_TO_CPUS(_i) rte_le_to_cpu_32(_i) argument
75 #define IXGBE_CPU_TO_BE16(_i) rte_cpu_to_be_16(_i) argument
76 #define IXGBE_CPU_TO_BE32(_i) rte_cpu_to_be_32(_i) argument
77 #define IXGBE_BE32_TO_CPU(_i) rte_be_to_cpu_32(_i) argument
/f-stack/freebsd/sys/
H A Dcounter.h46 for (int _i = 0; _i < (n); _i++) \
47 (a)[_i] = counter_u64_alloc(wait); \
51 for (int _i = 0; _i < (n); _i++) \
52 counter_u64_free((a)[_i]); \
56 for (int _i = 0; _i < (n); _i++) \
57 ((uint64_t *)(dstp))[_i] = counter_u64_fetch((a)[_i]);\
61 for (int _i = 0; _i < (n); _i++) \
62 counter_u64_zero((a)[_i]); \
H A Dpcpu.h139 u_int _i; \
143 CPU_FOREACH(_i) { \
144 sum += *DPCPU_ID_PTR(_i, n); \
151 u_int _i; \
155 CPU_FOREACH(_i) { \
156 sum += (DPCPU_ID_PTR(_i, n))->var; \
162 u_int _i; \
164 CPU_FOREACH(_i) { \
165 bzero(DPCPU_ID_PTR(_i, n), sizeof(*DPCPU_PTR(n))); \
H A Dqmath.h224 int _i; \
242 *(_r + _i) = *(_s - _i - 1); /* Copy RHS char to LHS. */\
245 _i = (prec); \
246 if (_i != 0 && _r != NULL) { \
252 if (_i < 0 || _i > (int)Q_NFBITS(q)) \
253 _i = Q_NFBITS(q); \
297 int _i = sizeof(""#dfv) - 1; \
303 _i = (nfbits) - 1; \
304 while (_i >= 0) { \
306 _bfv |= 1ULL << _i; \
[all …]
/f-stack/freebsd/contrib/ngatm/netnatm/sig/
H A Dunimkmsg.h113 u_int _i, _j; \
115 for(_i = _j = 0; _i < 2; _i++) \
118 (U)->u.release_compl.cause[_i]; \
119 for(_i = _j = 0; _i < UNI_NUM_IE_GIT; _i++) \
122 (U)->u.release_compl.git[_i]; \
131 u_int _i, _j; \
139 for(_i = _j = 0; _i < UNI_NUM_IE_GIT; _i++) \
142 (U)->u.drop_party_ack.git[_i]; \
147 u_int _i, _j; \
155 for(_i = _j = 0; _i < UNI_NUM_IE_GIT; _i++) \
[all …]
/f-stack/dpdk/drivers/net/e1000/base/
H A De1000_regs.h258 #define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4)) argument
259 #define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ argument
261 #define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ argument
263 #define E1000_SHRAL(_i) (0x05438 + ((_i) * 8)) argument
264 #define E1000_SHRAH(_i) (0x0543C + ((_i) * 8)) argument
267 #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4)) argument
268 #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8)) argument
269 #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8)) argument
270 #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8)) argument
532 #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) argument
[all …]
H A De1000_ich8lan.h46 #define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8)) argument
47 #define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8)) argument
121 #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) argument
122 #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) argument
123 #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) argument
124 #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) argument
125 #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) argument
/f-stack/dpdk/drivers/common/iavf/
H A Diavf_register.h80 #define IAVF_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */ argument
81 #define IAVF_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _IN… argument
85 #define IAVF_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ argument
86 #define IAVF_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */ argument
88 #define IAVF_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ argument
/f-stack/dpdk/drivers/net/igc/base/
H A Digc_regs.h250 #define IGC_PSRTYPE(_i) (0x05480 + ((_i) * 4)) argument
262 #define IGC_SHRAL(_i) (0x05438 + ((_i) * 8)) argument
263 #define IGC_SHRAH(_i) (0x0543C + ((_i) * 8)) argument
264 #define IGC_IP4AT_REG(_i) (0x05840 + ((_i) * 8)) argument
265 #define IGC_IP6AT_REG(_i) (0x05880 + ((_i) * 4)) argument
266 #define IGC_WUPM_REG(_i) (0x05A00 + ((_i) * 4)) argument
267 #define IGC_FFMT_REG(_i) (0x09000 + ((_i) * 8)) argument
268 #define IGC_FFVT_REG(_i) (0x09800 + ((_i) * 8)) argument
269 #define IGC_FFLT_REG(_i) (0x05F00 + ((_i) * 8)) argument
542 #define IGC_RETA(_i) (0x05C00 + ((_i) * 4)) argument
[all …]
H A Digc_ich8lan.h46 #define IGC_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8)) argument
47 #define IGC_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8)) argument
120 #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) argument
121 #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) argument
122 #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) argument
123 #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) argument
124 #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) argument
/f-stack/app/redis-5.0.5/src/
H A Dquicklist.c1626 for (int _i = 0; _i < (int)option_count; _i++) { in quicklistTest() local
1654 options[_i]) { in quicklistTest()
1668 options[_i]) { in quicklistTest()
1682 options[_i]) { in quicklistTest()
1696 options[_i]) { in quicklistTest()
1729 options[_i]) { in quicklistTest()
1983 f, options[_i]) { in quicklistTest()
2054 options[_i]) { in quicklistTest()
2073 options[_i]) { in quicklistTest()
2092 options[_i]) { in quicklistTest()
[all …]
/f-stack/freebsd/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300phy.h331 #define AR_PHY_BBB_RX_CTRL(_i) AR_BBB_OFFSET(BB_bbb_rx_ctrl_##_i) argument
549 #define AR_PHY_RF_CTL(_i) AR_SM_OFFSET(BB_tx_timing_##_i) argument
773 #define AR_PHY_TX_FIR(_i) AR_SM_OFFSET(BB_bbb_txfir_##_i) argument
780 #define AR_PHY_POWER_TX_RATE(_i) AR_SM_OFFSET(BB_powertx_rate##_i) argument
835 #define AR_PHY_TXGAIN_TAB(_i) AR_SM_OFFSET(BB_tx_gain_tab_##_i) /* values 1-22 */ argument
836 #define AR_PHY_TXGAIN_TAB_PAL(_i) AR_SM_OFFSET(BB_tx_gain_tab_pal_##_i) /* values 1-22 */ argument
1431 #define AR_PHY_SWITCH_CHAIN(_i) (AR_PHY_SWITCH_CHAIN_0 + (AR_PHY_CHAIN_OFFSET * (_i))) argument
1432 #define AR_PHY_EXT_ATTEN_CTL(_i) (AR_PHY_EXT_ATTEN_CTL_0 + (AR_PHY_CHAIN_OFFSET * (_i))) argument
1434 #define AR_PHY_RXGAIN(_i) (AR_PHY_FORCEMAX_GAINS_0 + (AR_PHY_CHAIN_OFFSET * (_i))) argument
1435 #define AR_PHY_TPCRG5(_i) (AR_PHY_TPC_5_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) argument
[all …]
H A Dar9300reg.h463 #define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2)) argument
482 #define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2)) argument
490 #define AR_QRDYTIMECFG(_i) (AR_Q0_RDYTIMECFG + ((_i)<<2)) argument
507 #define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2)) argument
528 #define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<2)) argument
566 #define AR_DQCUMASK(_i) (AR_D0_QCUMASK + ((_i)<<2)) argument
587 #define AR_DRETRY_LIMIT(_i) (AR_D0_RETRY_LIMIT + ((_i)<<2)) argument
603 #define AR_DCHNTIME(_i) (AR_D0_CHNTIME + ((_i)<<2)) argument
621 #define AR_DMISC(_i) (AR_D0_MISC + ((_i)<<2)) argument
664 #define AR_DLCL_IFS(_i) (AR_D0_LCL_IFS + ((_i)<<2)) argument
[all …]
/f-stack/freebsd/mips/mediatek/
H A Dmtk_intr_gic.c68 #define MTK_MAPPIN(_i) (0x0500 + (4 * (_i))) argument
69 #define MTK_MAPVPE(_i, _v) (0x2000 + (32 * (_i)) + (((_v) / 32) * 4)) argument
75 #define MTK_PIN_BITS(_i) ((1 << 31) | (_i)) argument
/f-stack/freebsd/mips/broadcom/
H A Dbcm_mips74kreg.h53 #define BCM_MIPS74K_INTR_SEL_FLAG(_i) (1<<_i) argument
/f-stack/dpdk/drivers/net/qede/base/
H A Decore_iov_api.h769 #define ecore_for_each_vf(_p_hwfn, _i) \ argument
770 for (_i = ecore_iov_get_next_active_vf(_p_hwfn, 0); \
771 _i < MAX_NUM_VFS_K2; \
772 _i = ecore_iov_get_next_active_vf(_p_hwfn, _i + 1))
/f-stack/dpdk/app/test/
H A Dtest_link_bonding_rssconf.c111 #define FOR_EACH(_i, _item, _array, _size) \ argument
112 for (_i = 0, _item = &_array[0]; _i < _size && (_item = &_array[_i]); _i++)
119 #define FOR_EACH_PORT(_i, _port) \ argument
120 FOR_EACH(_i, _port, test_params.slave_ports, \
/f-stack/freebsd/net/
H A Dif_vlan.c137 size_t _i; \
138 for (_i = 0; _i < VLAN_ARRAY_SIZE; _i++) \
139 if (((_ifv) = (_trunk)->vlans[_i]) != NULL)
143 size_t _i; \
144 for (_i = 0; _i < (1 << (_trunk)->hwidth); _i++) \
156 size_t _i; \
157 for (_i = 0; !(_cond) && _i < VLAN_ARRAY_SIZE; _i++) \
158 if (((_ifv) = (_trunk)->vlans[_i]))
169 size_t _i; \
171 for (_i = 0; \
[all …]
/f-stack/freebsd/net/route/
H A Dnhop_utils.h155 for (uint32_t _i = 0; _i < (_head)->hash_size; _i++) { \
156 for (_x = CHT_FIRST(_head, _i); _x; _x = _PX##_next(_x))

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