Searched refs:ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX (Results 1 – 2 of 2) sorted by relevance
348 for (div1 = 1; div1 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX; div1++) { in zy7_pl_fclk_set_freq()351 if (div0 > 0 && div0 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX && in zy7_pl_fclk_set_freq()357 if (div1 > ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX) in zy7_pl_fclk_set_freq()
157 #define ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX 0x3f macro