1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
5 * reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * NETLOGIC_BSD
31 * $FreeBSD$
32 */
33
34 #ifndef __NLM_HAL_IOMAP_H__
35 #define __NLM_HAL_IOMAP_H__
36
37 #define XLP_DEFAULT_IO_BASE 0x18000000
38 #define NMI_BASE 0xbfc00000
39 #define XLP_IO_CLK 133333333
40
41 #define XLP_L2L3_CACHELINE_SIZE 64
42 #define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */
43 #define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE)
44 #define XLP_PCIE_BUS_BLK_SIZE (256 * XLP_PCIE_DEV_BLK_SIZE)
45 #define XLP_IO_SIZE (64 << 20) /* ECFG space size */
46 #define XLP_IO_PCI_HDRSZ 0x100
47 #define XLP_IO_DEV(node, dev) ((dev) + (node) * 8)
48 #define XLP_HDR_OFFSET(node, bus, dev, fn) (((bus) << 20) | \
49 ((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12))
50
51 #define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0)
52 /* coherent inter chip */
53 #define XLP_IO_CIC0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 1)
54 #define XLP_IO_CIC1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 2)
55 #define XLP_IO_CIC2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 3)
56 #define XLP_IO_PIC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 4)
57
58 #define XLP_IO_PCIE_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 1, i)
59 #define XLP_IO_PCIE0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 0)
60 #define XLP_IO_PCIE1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 1)
61 #define XLP_IO_PCIE2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 2)
62 #define XLP_IO_PCIE3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 3)
63
64 #define XLP_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 2, i)
65 #define XLP_IO_USB_EHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 0)
66 #define XLP_IO_USB_OHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 1)
67 #define XLP_IO_USB_OHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 2)
68 #define XLP_IO_USB_EHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 3)
69 #define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4)
70 #define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5)
71
72 #define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0)
73 #define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1)
74 #define XLP_IO_SATA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 2)
75
76 #define XLP_IO_CMS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 0)
77
78 #define XLP_IO_DMA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 0)
79 #define XLP_IO_SEC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 1)
80 #define XLP_IO_RSA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 2)
81 #define XLP_IO_CMP_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 3)
82 #define XLP_IO_SRIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 4)
83 #define XLP_IO_REGEX_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 5)
84
85 #define XLP_IO_UART_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, i)
86 #define XLP_IO_UART0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 0)
87 #define XLP_IO_UART1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 1)
88 #define XLP_IO_I2C_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, 2 + i)
89 #define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2)
90 #define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3)
91 #define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4)
92 /* system management */
93 #define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5)
94 #define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6)
95
96 #define XLP_IO_NOR_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 0)
97 #define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1)
98 #define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2)
99 /* SD flash */
100 #define XLP_IO_SD_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3)
101 #define XLP_IO_MMC_OFFSET(node, slot) \
102 ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)
103
104 /* PCI config header register id's */
105 #define XLP_PCI_CFGREG0 0x00
106 #define XLP_PCI_CFGREG1 0x01
107 #define XLP_PCI_CFGREG2 0x02
108 #define XLP_PCI_CFGREG3 0x03
109 #define XLP_PCI_CFGREG4 0x04
110 #define XLP_PCI_CFGREG5 0x05
111 #define XLP_PCI_DEVINFO_REG0 0x30
112 #define XLP_PCI_DEVINFO_REG1 0x31
113 #define XLP_PCI_DEVINFO_REG2 0x32
114 #define XLP_PCI_DEVINFO_REG3 0x33
115 #define XLP_PCI_DEVINFO_REG4 0x34
116 #define XLP_PCI_DEVINFO_REG5 0x35
117 #define XLP_PCI_DEVINFO_REG6 0x36
118 #define XLP_PCI_DEVINFO_REG7 0x37
119 #define XLP_PCI_DEVSCRATCH_REG0 0x38
120 #define XLP_PCI_DEVSCRATCH_REG1 0x39
121 #define XLP_PCI_DEVSCRATCH_REG2 0x3a
122 #define XLP_PCI_DEVSCRATCH_REG3 0x3b
123 #define XLP_PCI_MSGSTN_REG 0x3c
124 #define XLP_PCI_IRTINFO_REG 0x3d
125 #define XLP_PCI_UCODEINFO_REG 0x3e
126 #define XLP_PCI_SBB_WT_REG 0x3f
127
128 /* PCI IDs for SoC device */
129 #define PCI_VENDOR_NETLOGIC 0x184e
130
131 #define PCI_DEVICE_ID_NLM_ROOT 0x1001
132 #define PCI_DEVICE_ID_NLM_ICI 0x1002
133 #define PCI_DEVICE_ID_NLM_PIC 0x1003
134 #define PCI_DEVICE_ID_NLM_PCIE 0x1004
135 #define PCI_DEVICE_ID_NLM_EHCI 0x1007
136 #define PCI_DEVICE_ID_NLM_ILK 0x1008
137 #define PCI_DEVICE_ID_NLM_NAE 0x1009
138 #define PCI_DEVICE_ID_NLM_POE 0x100A
139 #define PCI_DEVICE_ID_NLM_FMN 0x100B
140 #define PCI_DEVICE_ID_NLM_RAID 0x100D
141 #define PCI_DEVICE_ID_NLM_SAE 0x100D
142 #define PCI_DEVICE_ID_NLM_RSA 0x100E
143 #define PCI_DEVICE_ID_NLM_CMP 0x100F
144 #define PCI_DEVICE_ID_NLM_UART 0x1010
145 #define PCI_DEVICE_ID_NLM_I2C 0x1011
146 #define PCI_DEVICE_ID_NLM_NOR 0x1015
147 #define PCI_DEVICE_ID_NLM_NAND 0x1016
148 #define PCI_DEVICE_ID_NLM_MMC 0x1018
149
150 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
151
152 #define nlm_read_pci_reg(b, r) nlm_read_reg(b, r)
153 #define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v)
154
155 extern uint64_t xlp_sys_base;
156 extern uint64_t xlp_pic_base;
157
158 static __inline__ int
nlm_dev_exists(uint32_t devoffset)159 nlm_dev_exists(uint32_t devoffset)
160 {
161 uint64_t pcibase = nlm_pcicfg_base(devoffset);
162
163 return (nlm_read_reg(pcibase, XLP_PCI_CFGREG0) != 0xffffffff);
164 }
165
166 static __inline__ int
nlm_qidstart(uint64_t pcibase)167 nlm_qidstart(uint64_t pcibase)
168 {
169 return (nlm_read_reg(pcibase, XLP_PCI_MSGSTN_REG) & 0xffff);
170 }
171
172 static __inline__ int
nlm_qnum(uint64_t pcibase)173 nlm_qnum(uint64_t pcibase)
174 {
175 return (nlm_read_reg(pcibase, XLP_PCI_MSGSTN_REG) >> 16);
176 }
177
178 static __inline__ int
nlm_irtstart(uint64_t pcibase)179 nlm_irtstart(uint64_t pcibase)
180 {
181 return (nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff);
182 }
183
184 static __inline__ int
nlm_irtnum(uint64_t pcibase)185 nlm_irtnum(uint64_t pcibase)
186 {
187 return (nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) >> 16);
188 }
189
190 static __inline__ int
nlm_num_uengines(uint64_t pcibase)191 nlm_num_uengines(uint64_t pcibase)
192 {
193 return nlm_read_reg(pcibase, XLP_PCI_UCODEINFO_REG);
194 }
195
196 /*
197 * Find node on which a given Soc device is located.
198 * input is the pci device (slot) number.
199 */
200 static __inline__ int
nlm_get_device_node(int device)201 nlm_get_device_node(int device)
202 {
203 return (device / 8);
204 }
205
206 #endif /* !LOCORE or !__ASSEMBLY */
207
208 #endif /* __NLM_HAL_IOMAP_H__ */
209