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Searched refs:WRITE4 (Results 1 – 25 of 46) sorted by relevance

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/f-stack/freebsd/arm/freescale/vybrid/
H A Dvf_dcu4.c232 WRITE4(sc, DCU_INT_STATUS, reg); in dcu_intr()
297 WRITE4(sc, DCU_DISP_SIZE, reg); in dcu_init()
302 WRITE4(sc, DCU_HSYN_PARA, reg); in dcu_init()
307 WRITE4(sc, DCU_VSYN_PARA, reg); in dcu_init()
309 WRITE4(sc, DCU_BGND, 0); in dcu_init()
313 WRITE4(sc, DCU_SYNPOL, reg); in dcu_init()
319 WRITE4(sc, DCU_THRESHOLD, reg); in dcu_init()
322 WRITE4(sc, DCU_INT_MASK, 0xffffffff); in dcu_init()
339 WRITE4(sc, DCU_CTRLDESCLn_1(0), reg); in dcu_init()
340 WRITE4(sc, DCU_CTRLDESCLn_2(0), 0x0); in dcu_init()
[all …]
H A Dvf_anadig.c143 WRITE4(sc, pll_ctrl, reg); in enable_pll()
151 WRITE4(sc, pll_ctrl, reg); in enable_pll()
171 WRITE4(sc, ANADIG_PLL4_CTRL, reg); in pll4_configure_output()
172 WRITE4(sc, ANADIG_PLL4_NUM, mfn); in pll4_configure_output()
173 WRITE4(sc, ANADIG_PLL4_DENOM, mfd); in pll4_configure_output()
211 WRITE4(sc, ANADIG_REG_3P0, reg); in anadig_attach()
216 WRITE4(sc, USB_MISC(0), reg); in anadig_attach()
220 WRITE4(sc, USB_MISC(1), reg); in anadig_attach()
H A Dvf_spi.c169 WRITE4(sc, SPI_MCR, reg); in spi_attach()
173 WRITE4(sc, SPI_RSER, reg); in spi_attach()
177 WRITE4(sc, SPI_MCR, reg); in spi_attach()
195 WRITE4(sc, SPI_CTAR0, reg); in spi_attach()
200 WRITE4(sc, SPI_CTAR0, reg); in spi_attach()
225 WRITE4(sc, SPI_PUSHR, wreg); in spi_txrx()
236 WRITE4(sc, SPI_SR, reg); in spi_txrx()
H A Dvf_adc.c177 WRITE4(sc, ADC_HC0, reg); in adc_enable()
214 WRITE4(sc, ADC_CFG, reg); in adc_attach()
219 WRITE4(sc, ADC_GC, reg); in adc_attach()
224 WRITE4(sc, ADC_HC0, reg); in adc_attach()
H A Dvf_sai.c362 WRITE4(sc, I2S_TCR2, reg); in sai_configure_clock()
627 WRITE4(sc, I2S_TCSR, reg); in setup_sai()
631 WRITE4(sc, I2S_TCR3, reg); in setup_sai()
634 WRITE4(sc, I2S_TCR1, reg); in setup_sai()
640 WRITE4(sc, I2S_TCR2, reg); in setup_sai()
646 WRITE4(sc, I2S_TCR3, reg); in setup_sai()
655 WRITE4(sc, I2S_TCR4, reg); in setup_sai()
664 WRITE4(sc, I2S_TCR5, reg); in setup_sai()
670 WRITE4(sc, I2S_TCSR, reg); in setup_sai()
H A Dvf_ccm.c383 WRITE4(sc, clk->sel_reg, reg); in set_clock()
390 WRITE4(sc, clk->reg, reg); in set_clock()
464 WRITE4(sc, CCM_CCR, reg); in ccm_attach()
478 WRITE4(sc, CCM_CCGR(i), 0xffffffff); in ccm_attach()
H A Dvf_gpio.c285 WRITE4(sc, GPIO_PTOR(i), (1 << (i % 32))); in vf_gpio_pin_toggle()
308 WRITE4(sc, GPIO_PCOR(pin->gp_pin), in vf_gpio_pin_configure()
353 WRITE4(sc, GPIO_PSOR(i), (1 << (i % 32))); in vf_gpio_pin_set()
355 WRITE4(sc, GPIO_PCOR(i), (1 << (i % 32))); in vf_gpio_pin_set()
/f-stack/freebsd/arm/freescale/imx/
H A Dimx6_sdma.c67 #define WRITE4(_sc, _reg, _val) \ macro
100 WRITE4(sc, SDMAARM_INTR, pending); in sdma_intr()
222 WRITE4(sc, SDMAARM_EVTOVR, reg); in sdma_overrides()
230 WRITE4(sc, SDMAARM_HOSTOVR, reg); in sdma_overrides()
238 WRITE4(sc, SDMAARM_DSPOVR, reg); in sdma_overrides()
330 WRITE4(sc, SDMAARM_HSTART, 1); in sdma_configure()
347 WRITE4(sc, SDMAARM_INTR, ret); in sdma_configure()
395 WRITE4(sc, SDMAARM_MC0PTR, 0); in boot_firmware()
431 WRITE4(sc, SDMAARM_CONFIG, 0); in boot_firmware()
442 WRITE4(sc, SDMAARM_HSTART, 1); in boot_firmware()
[all …]
H A Dimx_gpt.c54 #define WRITE4(_sc, _r, _v) \ macro
195 WRITE4(sc, IMX_GPT_CR, 0); in imx_gpt_attach()
196 WRITE4(sc, IMX_GPT_IR, 0); in imx_gpt_attach()
206 WRITE4(sc, IMX_GPT_CR, ctlreg); in imx_gpt_attach()
229 WRITE4(sc, IMX_GPT_PR, prescale); in imx_gpt_attach()
232 WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL); in imx_gpt_attach()
259 WRITE4(sc, IMX_GPT_OCR3, 0); in imx_gpt_attach()
302 WRITE4(sc, IMX_GPT_IR, sc->ir_reg); in imx_gpt_timer_start()
308 WRITE4(sc, IMX_GPT_IR, sc->ir_reg); in imx_gpt_timer_start()
332 WRITE4(sc, IMX_GPT_IR, sc->ir_reg); in imx_gpt_timer_stop()
[all …]
H A Dimx6_audmux.c57 #define WRITE4(_sc, _reg, _val) \ macro
108 WRITE4(sc, AUDMUX_PTCR(audmux_port), reg); in audmux_configure()
112 WRITE4(sc, AUDMUX_PDCR(audmux_port), reg); in audmux_configure()
H A Dimx_gpio.c74 #define WRITE4(_sc, _r, _v) \ macro
79 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
385 WRITE4(sc, reg, wrk); in gpio_pic_setup_intr()
387 WRITE4(sc, IMX_GPIO_ISR_REG, (1u << irq)); in gpio_pic_setup_intr()
439 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); in gpio_pic_post_filter()
453 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); in gpio_pic_post_ithread()
710 WRITE4(sc, IMX_GPIO_DR_REG, in imx51_gpio_pin_toggle()
733 WRITE4(sc, IMX_GPIO_DR_REG, in imx51_gpio_pin_access_32()
774 WRITE4(sc, IMX_GPIO_DR_REG, in imx51_gpio_pin_config_32()
776 WRITE4(sc, IMX_GPIO_OE_REG, in imx51_gpio_pin_config_32()
[all …]
/f-stack/freebsd/arm/altera/socfpga/
H A Dsocfpga_a10_manager.c178 WRITE4(sc, IMGCFG_CTRL_02, reg); in fpga_open()
182 WRITE4(sc, IMGCFG_CTRL_02, reg); in fpga_open()
187 WRITE4(sc, IMGCFG_CTRL_01, reg); in fpga_open()
191 WRITE4(sc, IMGCFG_CTRL_00, reg); in fpga_open()
196 WRITE4(sc, IMGCFG_CTRL_01, reg); in fpga_open()
201 WRITE4(sc, IMGCFG_CTRL_02, reg); in fpga_open()
211 WRITE4(sc, IMGCFG_CTRL_00, reg); in fpga_open()
216 WRITE4(sc, IMGCFG_CTRL_01, reg); in fpga_open()
224 WRITE4(sc, IMGCFG_CTRL_01, reg); in fpga_open()
278 WRITE4(sc, IMGCFG_CTRL_01, reg); in fpga_close()
[all …]
H A Dsocfpga_manager.c227 WRITE4(sc, FPGAMGR_CTRL, reg); in fpga_open()
232 WRITE4(sc, FPGAMGR_CTRL, reg); in fpga_open()
237 WRITE4(sc, FPGAMGR_CTRL, reg); in fpga_open()
248 WRITE4(sc, FPGAMGR_CTRL, reg); in fpga_open()
256 WRITE4(sc, GPIO_PORTA_EOI, PORTA_EOI_NS); in fpga_open()
261 WRITE4(sc, FPGAMGR_CTRL, reg); in fpga_open()
273 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1); in fpga_wait_dclk_pulses()
276 WRITE4(sc, FPGAMGR_DCLKCNT, npulses); in fpga_wait_dclk_pulses()
282 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1); in fpga_wait_dclk_pulses()
313 WRITE4(sc, FPGAMGR_CTRL, reg); in fpga_close()
[all …]
/f-stack/freebsd/arm64/rockchip/clk/
H A Drk_clk_pll.c58 #define WRITE4(_clk, off, val) \ macro
94 WRITE4(clk, sc->gate_offset, val); in rk_clk_pll_set_gate()
155 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_mux()
236 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_freq()
251 WRITE4(clk, sc->base_offset, reg); in rk3066_clk_pll_set_freq()
269 WRITE4(clk, sc->base_offset + 12, in rk3066_clk_pll_set_freq()
295 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_freq()
463 WRITE4(clk, sc->mode_reg, reg); in rk3328_clk_pll_set_freq()
470 WRITE4(clk, sc->base_offset, reg); in rk3328_clk_pll_set_freq()
502 WRITE4(clk, sc->mode_reg, reg); in rk3328_clk_pll_set_freq()
[all …]
/f-stack/freebsd/mips/mediatek/
H A Dmtk_intr_gic.c107 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->gic_res[0], (_reg), (_val)) macro
127 WRITE4(sc, MTK_INTENA, (1u << (irq))); in gic_irq_unmask()
134 WRITE4(sc, MTK_INTDIS, (1u << (irq))); in gic_irq_mask()
190 WRITE4(sc, MTK_INTDIS, 0xFFFFFFFF); in mtk_gic_attach()
193 WRITE4(sc, MTK_INTTRIG, 0x00000000); in mtk_gic_attach()
196 WRITE4(sc, MTK_INTPOL, 0xFFFFFFFF); in mtk_gic_attach()
202 WRITE4(sc, MTK_MAPPIN(i), MTK_PIN_BITS(0)); in mtk_gic_attach()
203 WRITE4(sc, MTK_MAPVPE(i, 0), MTK_VPE_BITS(0)); in mtk_gic_attach()
H A Dmtk_intr_v1.c105 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->pic_res[0], _reg, _val) macro
125 WRITE4(sc, MTK_INTENA, (1u << (irq))); in pic_irq_unmask()
132 WRITE4(sc, MTK_INTDIS, (1u << (irq))); in pic_irq_mask()
186 WRITE4(sc, MTK_INTDIS, 0x7FFFFFFF); in mtk_pic_attach()
189 WRITE4(sc, MTK_INTENA, 0x80000000); in mtk_pic_attach()
192 WRITE4(sc, MTK_INTTYPE, 0x00000000); in mtk_pic_attach()
H A Dmtk_intr_v2.c100 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->pic_res[0], _reg, _val) macro
120 WRITE4(sc, MTK_INTENA, (1u << (irq))); in pic_irq_unmask()
127 WRITE4(sc, MTK_INTDIS, (1u << (irq))); in pic_irq_mask()
181 WRITE4(sc, MTK_INTDIS, 0xFFFFFFFF); in mtk_pic_attach()
184 WRITE4(sc, MTK_INTENA, 0x00000000); in mtk_pic_attach()
187 WRITE4(sc, MTK_INTTYPE, 0xFFFFFFFF); in mtk_pic_attach()
/f-stack/freebsd/mips/ingenic/
H A Djz4780_intr.c92 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->pic_res[0], _reg, _val) macro
111 WRITE4(sc, JZ_ICMCR0, (1u << irq)); in pic_irq_unmask()
113 WRITE4(sc, JZ_ICMCR1, (1u << (irq - 32))); in pic_irq_unmask()
120 WRITE4(sc, JZ_ICMSR0, (1u << irq)); in pic_irq_mask()
122 WRITE4(sc, JZ_ICMSR1, (1u << (irq - 32))); in pic_irq_mask()
177 WRITE4(sc, JZ_ICMR0, 0xFFFFFFFF); in jz4780_pic_attach()
178 WRITE4(sc, JZ_ICMR1, 0xFFFFFFFF); in jz4780_pic_attach()
H A Djz4780_pdma.c138 WRITE4(sc, PDMA_DIRQP, 0); in pdma_intr()
149 WRITE4(sc, PDMA_DCS(chan->index), 0); in pdma_intr()
214 WRITE4(sc, PDMA_DMAC, reg); in pdma_attach()
216 WRITE4(sc, PDMA_DMACP, 0); in pdma_attach()
241 WRITE4(sc, PDMA_DCS(chan->index), DCS_DES8); in chan_start()
242 WRITE4(sc, PDMA_DDA(chan->index), in chan_start()
245 WRITE4(sc, PDMA_DDS, (1 << chan->index)); in chan_start()
248 WRITE4(sc, PDMA_DCS(chan->index), (DCS_DES8 | DCS_CTE)); in chan_start()
258 WRITE4(sc, PDMA_DCS(chan->index), 0); in chan_stop()
/f-stack/freebsd/arm/allwinner/clkng/
H A Daw_clk_nkmp.c67 #define WRITE4(_clk, off, val) \ macro
116 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_gate()
137 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_mux()
212 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq_scale()
219 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq_scale()
227 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq_scale()
233 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq_scale()
240 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq_scale()
300 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq()
308 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq()
H A Daw_clk_mipi.c70 #define WRITE4(_clk, off, val) \ macro
114 WRITE4(clk, sc->offset, val); in aw_clk_mipi_set_gate()
183 WRITE4(clk, sc->offset, val); in aw_clk_mipi_set_freq()
196 WRITE4(clk, sc->offset, val); in aw_clk_mipi_set_freq()
200 WRITE4(clk, sc->offset, val); in aw_clk_mipi_set_freq()
H A Daw_clk_m.c64 #define WRITE4(_clk, off, val) \ macro
111 WRITE4(clk, sc->offset, val); in aw_clk_m_set_gate()
132 WRITE4(clk, sc->offset, val); in aw_clk_m_set_mux()
219 WRITE4(clk, sc->offset, val); in aw_clk_m_set_freq()
H A Daw_clk_frac.c72 #define WRITE4(_clk, off, val) \ macro
121 WRITE4(clk, sc->offset, val); in aw_clk_frac_set_gate()
143 WRITE4(clk, sc->offset, val); in aw_clk_frac_set_mux()
272 WRITE4(clk, sc->offset, val); in aw_clk_frac_set_freq()
293 WRITE4(clk, sc->offset, val); in aw_clk_frac_set_freq()
297 WRITE4(clk, sc->offset, val); in aw_clk_frac_set_freq()
/f-stack/freebsd/arm/ti/clk/
H A Dti_clk_clkctrl.c75 #define WRITE4(_clk, off, val) \ macro
119 WRITE4(clk, sc->register_offset, val); in ti_clkctrl_set_gdbclk_gate()
158 WRITE4(clk, sc->register_offset, MODULEMODE_ENABLE); in ti_clkctrl_set_gate()
160 WRITE4(clk, sc->register_offset, MODULEMODE_DISABLE); in ti_clkctrl_set_gate()
H A Dti_clk_dpll.c67 #define WRITE4(_clk, off, val) \ macro
218 WRITE4(clk, sc->ti_clkmode_offset, DPLL_EN_MN_BYPASS_MODE); in ti_dpll_clk_set_freq()
242 WRITE4(clk, sc->ti_clksel_offset, val); in ti_dpll_clk_set_freq()
251 WRITE4(clk, sc->ti_clkmode_offset, DPLL_EN_LOCK_MODE); in ti_dpll_clk_set_freq()

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