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Searched refs:WR4 (Results 1 – 25 of 62) sorted by relevance

123

/f-stack/freebsd/arm/freescale/imx/
H A Dimx6_ccm.c97 WR4(sc, CCM_CCGR0, reg); in ccm_init_gates()
102 WR4(sc, CCM_CCGR1, reg); in ccm_init_gates()
109 WR4(sc, CCM_CCGR2, reg); in ccm_init_gates()
114 WR4(sc, CCM_CCGR3, reg); in ccm_init_gates()
119 WR4(sc, CCM_CCGR4, reg); in ccm_init_gates()
124 WR4(sc, CCM_CCGR5, reg); in ccm_init_gates()
129 WR4(sc, CCM_CCGR6, reg); in ccm_init_gates()
181 WR4(sc, CCM_CGPR, reg); in ccm_attach()
184 WR4(sc, CCM_CLPCR, reg); in ccm_attach()
455 WR4(sc, CCM_CCGR3, reg); in imx_ccm_ipu_enable()
[all …]
H A Dimx_epit.c142 WR4(struct epit_softc *sc, bus_size_t offset, uint32_t value) in WR4() function
203 WR4(sc, EPIT_LR, 0xffffffff); in epit_tc_attach()
204 WR4(sc, EPIT_CR, sc->ctlreg | EPIT_CR_EN); in epit_tc_attach()
234 WR4(sc, EPIT_CR, sc->ctlreg); in epit_et_start()
235 WR4(sc, EPIT_SR, EPIT_SR_OCIF); in epit_et_start()
247 WR4(sc, EPIT_LR, ticks); in epit_et_start()
261 WR4(sc, EPIT_CR, sc->ctlreg); in epit_et_stop()
286 WR4(sc, EPIT_CR, sc->ctlreg); in epit_intr()
450 WR4(sc, EPIT_CR, 0); in epit_attach()
H A Dimx_iomux.c114 WR4(struct iomux_softc *sc, bus_size_t off, uint32_t val) in WR4() function
143 WR4(sc, reg, val); in iomux_configure_input()
165 WR4(sc, cfg->mux_reg, cfg->mux_val | sion); in iomux_configure_pins()
168 WR4(sc, cfg->padconf_reg, cfg->padconf_val); in iomux_configure_pins()
289 WR4(iomux_sc, regaddr, val); in imx_iomux_gpr_set()
306 WR4(iomux_sc, regaddr, val); in imx_iomux_gpr_set_masked()
/f-stack/freebsd/arm/nvidia/drm2/
H A Dtegra_dc.c434 WR4(sc, DC_WIN_DDA_INCREMENT, in dc_setup_window()
444 WR4(sc, DC_WIN_LINE_STRIDE, in dc_setup_window()
667 WR4(sc, DC_DISP_REF_TO_SYNC, in dc_crtc_mode_set()
671 WR4(sc, DC_DISP_SYNC_WIDTH, in dc_crtc_mode_set()
675 WR4(sc, DC_DISP_BACK_PORCH, in dc_crtc_mode_set()
679 WR4(sc, DC_DISP_FRONT_PORCH, in dc_crtc_mode_set()
683 WR4(sc, DC_DISP_DISP_ACTIVE, in dc_crtc_mode_set()
759 WR4(sc, DC_CMD_INT_MASK, in dc_crtc_prepare()
763 WR4(sc, DC_CMD_INT_ENABLE, in dc_crtc_prepare()
1212 WR4(sc, DC_CMD_INT_TYPE, in dc_init_client()
[all …]
H A Dtegra_hdmi.c556 WR4(sc, HDMI_NV_PDISP_AUDIO_N, in audio_setup()
567 WR4(sc, HDMI_NV_PDISP_HDMI_SPARE, in audio_setup()
572 WR4(sc, HDMI_NV_PDISP_AUDIO_N, val); in audio_setup()
574 WR4(sc, aval_reg, audio_aval); in audio_setup()
672 WR4(sc, HDMI_NV_PDISP_SOR_PLL0, val); in hdmi_sor_start()
677 WR4(sc, HDMI_NV_PDISP_SOR_PLL0, val); in hdmi_sor_start()
680 WR4(sc, HDMI_NV_PDISP_SOR_PWR, 0); in hdmi_sor_start()
707 WR4(sc, HDMI_NV_PDISP_SOR_STATE0, 0); in hdmi_sor_start()
714 WR4(sc, HDMI_NV_PDISP_SOR_STATE0, 0); in hdmi_sor_start()
744 WR4(sc, HDMI_NV_PDISP_INT_MASK, 0); in hdmi_disable()
[all …]
/f-stack/freebsd/arm/xilinx/
H A Duart_dev_cdnc.c59 #define WR4(bas, reg, value) \ macro
272 WR4(bas, CDNC_UART_CTRL_REG, in cdnc_uart_hw_init()
280 WR4(bas, CDNC_UART_MODEM_STAT_REG, in cdnc_uart_hw_init()
286 WR4(bas, CDNC_UART_RX_TIMEO_REG, 10); in cdnc_uart_hw_init()
292 WR4(bas, CDNC_UART_CTRL_REG, in cdnc_uart_hw_init()
340 WR4(bas, CDNC_UART_FIFO, c); in cdnc_uart_putc()
448 WR4(bas, CDNC_UART_IEN_REG, in cdnc_uart_bus_attach()
520 WR4(bas, CDNC_UART_ISTAT_REG, in cdnc_uart_bus_receive()
595 WR4(bas, CDNC_UART_MODEM_STAT_REG, in cdnc_uart_bus_ipend()
684 WR4(&sc->sc_bas, CDNC_UART_IEN_REG, in cdnc_uart_bus_grab()
[all …]
H A Dzy7_qspi.c253 WR4(sc, ZY7_QSPI_TXD1_REG, data); in zy7_qspi_write_fifo()
256 WR4(sc, ZY7_QSPI_TXD2_REG, data); in zy7_qspi_write_fifo()
259 WR4(sc, ZY7_QSPI_TXD3_REG, data); in zy7_qspi_write_fifo()
323 WR4(sc, ZY7_QSPI_INTR_DIS_REG, in zy7_qspi_abort_transfer()
353 WR4(sc, ZY7_QSPI_INTR_STAT_REG, in zy7_qspi_intr()
363 WR4(sc, ZY7_QSPI_INTR_DIS_REG, in zy7_qspi_intr()
377 WR4(sc, ZY7_QSPI_INTR_STAT_REG, in zy7_qspi_intr()
392 WR4(sc, ZY7_QSPI_INTR_DIS_REG, in zy7_qspi_intr()
394 WR4(sc, ZY7_QSPI_INTR_EN_REG, in zy7_qspi_intr()
628 WR4(sc, ZY7_QSPI_EN_REG, 0); in zy7_qspi_detach()
[all …]
H A Dzy7_spi.c211 WR4(sc, ZY7_SPI_INTR_DIS_REG, in zy7_spi_abort_transfer()
241 WR4(sc, ZY7_SPI_INTR_STAT_REG, in zy7_spi_intr()
251 WR4(sc, ZY7_SPI_INTR_DIS_REG, in zy7_spi_intr()
261 WR4(sc, ZY7_SPI_INTR_STAT_REG, in zy7_spi_intr()
275 WR4(sc, ZY7_SPI_INTR_DIS_REG, in zy7_spi_intr()
277 WR4(sc, ZY7_SPI_INTR_EN_REG, in zy7_spi_intr()
324 WR4(sc, ZY7_SPI_TX_THRESH_REG, 32); in zy7_spi_init_hw()
325 WR4(sc, ZY7_SPI_RX_THRESH_REG, 1); in zy7_spi_init_hw()
329 WR4(sc, ZY7_SPI_INTR_DIS_REG, ~0); in zy7_spi_init_hw()
467 WR4(sc, ZY7_SPI_EN_REG, 0); in zy7_spi_detach()
[all …]
H A Dzy7_slcr.c127 WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC); in zy7_slcr_lock()
141 WR4(sc, ZY7_SLCR_REBOOT_STAT, in zy7_slcr_cpu_reset()
171 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0); in zy7_slcr_preload_pl()
202 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0); in zy7_slcr_postload_pl()
279 WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg); in zy7_pl_fclk_set_source()
371 WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg); in zy7_pl_fclk_set_freq()
450 WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0); in zy7_pl_fclk_enable()
451 WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 0); in zy7_pl_fclk_enable()
474 WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0); in zy7_pl_fclk_disable()
475 WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 1); in zy7_pl_fclk_disable()
[all …]
H A Dzy7_devcfg.c407 WR4(sc, ZY7_DEVCFG_CTRL, in zy7_devcfg_init_hw()
441 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); in zy7_devcfg_reset_pl()
450 WR4(sc, ZY7_DEVCFG_INT_MASK, ~0); in zy7_devcfg_reset_pl()
461 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); in zy7_devcfg_reset_pl()
478 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); in zy7_devcfg_reset_pl()
596 WR4(sc, ZY7_DEVCFG_DMA_SRC_ADDR, in zy7_devcfg_write()
599 WR4(sc, ZY7_DEVCFG_DMA_SRC_ADDR, in zy7_devcfg_write()
603 WR4(sc, ZY7_DEVCFG_DMA_SRC_LEN, (segsz+3)/4); in zy7_devcfg_write()
604 WR4(sc, ZY7_DEVCFG_DMA_DST_LEN, 0); in zy7_devcfg_write()
658 WR4(sc, ZY7_DEVCFG_INT_MASK, ~0); in zy7_devcfg_intr()
[all …]
H A Dzy7_gpio.c98 #define WR4(sc, off, val) bus_write_4((sc)->mem_res, (off), (val)) macro
207 WR4(sc, ZY7_GPIO_DIRM(pin >> 5), in zy7_gpio_pin_setflags()
211 WR4(sc, ZY7_GPIO_OEN(pin >> 5), in zy7_gpio_pin_setflags()
215 WR4(sc, ZY7_GPIO_OEN(pin >> 5), in zy7_gpio_pin_setflags()
220 WR4(sc, ZY7_GPIO_DIRM(pin >> 5), in zy7_gpio_pin_setflags()
222 WR4(sc, ZY7_GPIO_OEN(pin >> 5), in zy7_gpio_pin_setflags()
242 WR4(sc, ZY7_GPIO_MASK_DATA_MSW(pin >> 5), in zy7_gpio_pin_set()
246 WR4(sc, ZY7_GPIO_MASK_DATA_LSW(pin >> 5), in zy7_gpio_pin_set()
278 WR4(sc, ZY7_GPIO_DATA(pin >> 5), in zy7_gpio_pin_toggle()
/f-stack/freebsd/arm64/broadcom/genet/
H A Dif_genet.c463 WR4(sc, GENET_UMAC_CMD, 0); in gen_reset()
464 WR4(sc, GENET_UMAC_CMD, in gen_reset()
467 WR4(sc, GENET_UMAC_CMD, 0); in gen_reset()
471 WR4(sc, GENET_UMAC_MIB_CTRL, 0); in gen_reset()
477 WR4(sc, GENET_RBUF_CTRL, val); in gen_reset()
491 WR4(sc, GENET_UMAC_CMD, val); in gen_enable()
534 WR4(sc, GENET_TX_DMA_CTRL, val); in gen_dma_disable()
906 WR4(sc, GENET_UMAC_CMD, cmd); in gen_setup_rxfilter()
926 WR4(sc, GENET_UMAC_MAC0, val); in gen_set_enaddr()
928 WR4(sc, GENET_UMAC_MAC1, val); in gen_set_enaddr()
[all …]
/f-stack/freebsd/arm64/nvidia/tegra210/
H A Dtegra210_xusbpadctl.c1017 WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg); in usb3_port_init()
1056 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); in usb3_port_init()
1061 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); in usb3_port_init()
1066 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); in usb3_port_init()
1084 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); in pcie_enable()
1096 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); in pcie_disable()
1116 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); in sata_enable()
1128 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); in sata_disable()
1281 WR4(sc, XUSB_PADCTL_USB2_PORT_CAP, reg); in usb2_enable()
1384 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); in pad_common_enable()
[all …]
H A Dtegra210_clk_pll.c770 WR4(sc, PLLE_AUX, reg); in plle_enable()
826 WR4(sc, PLLE_AUX, reg); in plle_enable()
830 WR4(sc, PLLE_AUX, reg); in plle_enable()
1155 WR4(sc, PLLX_MISC_2, reg); in pllx_set_freq()
1161 WR4(sc, PLLX_MISC_2, reg); in pllx_set_freq()
1166 WR4(sc, PLLX_MISC_2, reg); in pllx_set_freq()
1189 WR4(sc, PLLX_MISC_2, reg); in pllx_set_freq()
1219 WR4(sc, PLLX_MISC, reg); in pllx_init()
1225 WR4(sc, PLLX_MISC_2, reg); in pllx_init()
1229 WR4(sc, PLLX_MISC_4, reg); in pllx_init()
[all …]
H A Dtegra210_pmc.c191 WR4(struct tegra210_pmc_softc *sc, bus_size_t r, uint32_t v) in WR4() function
246 WR4(sc, PMC_PWRGATE_TOGGLE, in tegra210_pmc_set_powergate()
273 WR4(sc, PMC_GPU_RG_CNTRL, 0); in tegra_powergate_remove_clamping()
509 WR4(sc, PMC_SCRATCH0, 0xDEADBEEF); in tegra210_pmc_check_secure()
514 WR4(sc, PMC_SCRATCH0, 0xBADC0DE); in tegra210_pmc_check_secure()
519 WR4(sc, PMC_SCRATCH0, orig); in tegra210_pmc_check_secure()
582 WR4(sc, PMC_CNTRL, reg); in tegra210_pmc_attach()
590 WR4(sc, PMC_CNTRL, reg); in tegra210_pmc_attach()
595 WR4(sc, PMC_CNTRL, reg); in tegra210_pmc_attach()
603 WR4(sc, PMC_IO_DPD_STATUS, reg); in tegra210_pmc_attach()
[all …]
/f-stack/freebsd/arm/nvidia/
H A Dtegra_i2c.c246 WR4(sc, I2C_FIFO_CONTROL, reg); in tegra_i2c_flush_fifo()
274 WR4(sc, I2C_CLK_DIVISOR, in tegra_i2c_setup_clk()
285 WR4(sc, I2C_BUS_CLEAR_CONFIG, in tegra_i2c_bus_clear()
300 WR4(sc, I2C_BUS_CLEAR_CONFIG,reg); in tegra_i2c_bus_clear()
334 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0); in tegra_i2c_hw_init()
376 WR4(sc, I2C_TX_PACKET_FIFO, reg); in tegra_i2c_tx()
425 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0); in tegra_i2c_intr()
469 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0); in tegra_i2c_intr()
486 WR4(sc, I2C_TX_PACKET_FIFO, tmp); in tegra_i2c_start_msg()
504 WR4(sc, I2C_TX_PACKET_FIFO, tmp); in tegra_i2c_start_msg()
[all …]
H A Dtegra_usbphy.c358 WR4(sc, IF_USB_SUSP_CTRL, val); in usbphy_utmi_enable()
362 WR4(sc, UTMIP_TX_CFG0, val); in usbphy_utmi_enable()
369 WR4(sc, UTMIP_HSRX_CFG0, val); in usbphy_utmi_enable()
374 WR4(sc, UTMIP_HSRX_CFG1, val); in usbphy_utmi_enable()
383 WR4(sc, UTMIP_MISC_CFG0, val); in usbphy_utmi_enable()
453 WR4(sc, UTMIP_XCVR_CFG0, val); in usbphy_utmi_enable()
461 WR4(sc, UTMIP_XCVR_CFG1, val); in usbphy_utmi_enable()
466 WR4(sc, UTMIP_BIAS_CFG1, val); in usbphy_utmi_enable()
473 WR4(sc, UTMIP_SPARE_CFG0, val); in usbphy_utmi_enable()
529 WR4(sc, UTMIP_XCVR_CFG0, val); in usbphy_utmi_disable()
[all …]
H A Dtegra_rtc.c77 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro
156 WR4(sc, RTC_SECONDS, tv.tv_sec); in tegra_rtc_settime()
171 WR4(sc, RTC_INTR_STATUS, status); in tegra_rtc_intr()
231 WR4(sc, RTC_SECONDS_ALARM0, 0); in tegra_rtc_attach()
232 WR4(sc, RTC_SECONDS_ALARM1, 0); in tegra_rtc_attach()
233 WR4(sc, RTC_INTR_STATUS, 0xFFFFFFFF); in tegra_rtc_attach()
234 WR4(sc, RTC_INTR_MASK, 0); in tegra_rtc_attach()
/f-stack/freebsd/arm64/qoriq/
H A Dqoriq_therm.c227 WR4(sc, TMU_TTRCR(i), ranges[i]); in qoriq_therm_fdt_calib()
238 WR4(sc, TMU_TTCFGR, calibs[i]); in qoriq_therm_fdt_calib()
239 WR4(sc, TMU_TSCFGR, calibs[i + 1]); in qoriq_therm_fdt_calib()
315 WR4(sc, TMU_TMR, 0); in qoriq_therm_attach()
319 WR4(sc, TMU_TIER, 0); in qoriq_therm_attach()
323 WR4(sc, TMUV1_TMTMIR, 0x0F); in qoriq_therm_attach()
327 WR4(sc, TMUV2_TEUMR(0), 0x51009c00); in qoriq_therm_attach()
329 WR4(sc, TMUV2_TMSAR(0), 0xE); in qoriq_therm_attach()
342 WR4(sc, TMU_TMR, 0x8C000000 | sites); in qoriq_therm_attach()
344 WR4(sc, TMUV2_TMSR, sites); in qoriq_therm_attach()
[all …]
/f-stack/freebsd/arm/nvidia/tegra124/
H A Dtegra124_xusbpadctl.c378 WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg); in usb3_port_init()
394 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); in usb3_port_init()
399 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); in usb3_port_init()
404 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); in usb3_port_init()
445 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); in pcie_powerup()
457 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); in pcie_powerdown()
504 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); in sata_powerup()
508 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); in sata_powerup()
520 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); in sata_powerdown()
649 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); in phy_powerup()
[all …]
H A Dtegra124_clk_pll.c422 WR4(sc, sc->base_reg, reg); in pll_enable()
435 WR4(sc, sc->base_reg, reg); in pll_disable()
572 WR4(sc, sc->base_reg, reg); in plle_enable()
577 WR4(sc, PLLE_AUX, reg); in plle_enable()
587 WR4(sc, sc->misc_reg, reg); in plle_enable()
592 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
598 WR4(sc, sc->base_reg, reg); in plle_enable()
611 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
614 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
631 WR4(sc, PLLE_AUX, reg); in plle_enable()
[all …]
/f-stack/freebsd/arm/broadcom/bcm2835/
H A Dbcm2835_sdhost.c281 WR4(sc, off & ~3, val32); in WR2()
292 WR4(sc, off & ~3, val32); in WR1()
348 WR4(sc, HC_POWER, 0); in bcm_sdhost_reset()
350 WR4(sc, HC_COMMAND, 0); in bcm_sdhost_reset()
351 WR4(sc, HC_ARGUMENT, 0); in bcm_sdhost_reset()
356 WR4(sc, HC_BLOCKSIZE, 0); in bcm_sdhost_reset()
364 WR4(sc, HC_DEBUG, dbg); in bcm_sdhost_reset()
368 WR4(sc, HC_POWER, 1); in bcm_sdhost_reset()
536 WR4(sc, HC_COMMAND, in bcm_sdhost_waitcommand_status()
618 WR4(sc, HC_COMMAND, in bcm_sdhost_intr()
[all …]
/f-stack/freebsd/arm64/rockchip/
H A Drk_tsadc.c416 WR4(sc, TSADC_INT_EN, val); in tsadc_init_tsensor()
423 WR4(sc, TSADC_AUTO_CON, val); in tsadc_init_tsensor()
427 WR4(sc, TSADC_COMP_INT(sensor->channel), val); in tsadc_init_tsensor()
430 WR4(sc, TSADC_INT_EN, val); in tsadc_init_tsensor()
446 WR4(sc, TSADC_AUTO_CON, val); in tsadc_init()
452 WR4(sc, TSADC_HIGHT_INT_DEBOUNCE, 4); in tsadc_init()
453 WR4(sc, TSADC_HIGHT_TSHUT_DEBOUNCE, 4); in tsadc_init()
474 WR4(sc, TSADC_HIGHT_INT_DEBOUNCE, 4); in tsadc_init()
475 WR4(sc, TSADC_HIGHT_TSHUT_DEBOUNCE, 4); in tsadc_init()
584 WR4(sc, TSADC_INT_PD, val); in tsadc_intr()
[all …]
/f-stack/freebsd/arm/allwinner/
H A Daw_thermal.c380 #define WR4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) macro
407 WR4(sc, THS_CALIB0, calib[0]); in aw_thermal_init()
409 WR4(sc, THS_CALIB1, calib[1]); in aw_thermal_init()
412 WR4(sc, THS_CTRL1, ADC_CALI_EN); in aw_thermal_init()
413 WR4(sc, THS_CTRL0, sc->conf->adc_acquire_time); in aw_thermal_init()
420 WR4(sc, THS_FILTER, sc->conf->filter); in aw_thermal_init()
423 WR4(sc, THS_INTS, RD4(sc, THS_INTS)); in aw_thermal_init()
427 WR4(sc, THS_CTRL2, RD4(sc, THS_CTRL2) | SENSOR_ENABLE_ALL); in aw_thermal_init()
461 WR4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4), val); in aw_thermal_setshut()
494 WR4(sc, THS_ALARM0_CTRL + (sensor * 4), val); in aw_thermal_setalarm()
[all …]
/f-stack/freebsd/arm/mv/
H A Dmv_thermal.c128 #define WR4(sc, reg, val) \ macro
170 WR4(sc, CONTROL0, reg); in mv_thermal_select_sensor()
186 WR4(sc, CONTROL0, reg); in mv_thermal_select_sensor()
192 WR4(sc, CONTROL0, reg); in mv_thermal_select_sensor()
233 WR4(sc, CONTROL0, reg); in ap806_init()
249 WR4(sc, CONTROL1, reg); in cp110_init()
254 WR4(sc, CONTROL0, reg); in cp110_init()

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