Searched refs:VM_MEMATTR_WRITE_BACK (Results 1 – 12 of 12) sorted by relevance
35 #define VM_MEMATTR_WRITE_BACK 2 macro43 #define VM_MEMATTR_DEFAULT VM_MEMATTR_WRITE_BACK
39 #define VM_MEMATTR_WRITE_BACK ((vm_memattr_t)MIPS_CCA_CACHED) macro40 #define VM_MEMATTR_DEFAULT VM_MEMATTR_WRITE_BACK
42 #define VM_MEMATTR_WRITE_BACK ((vm_memattr_t)PAT_WRITE_BACK) macro45 #define VM_MEMATTR_DEFAULT VM_MEMATTR_WRITE_BACK
45 #define VM_MEMATTR_WRITE_BACK VM_MEMATTR_WB_WA /* for DRM */ macro
433 mov x7, #VM_MEMATTR_WRITE_BACK483 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK))493 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK))738 MAIR_ATTR(MAIR_NORMAL_WB, VM_MEMATTR_WRITE_BACK) | \
208 mode = VM_MEMATTR_WRITE_BACK; in efi_create_1t1_map()
1189 return (VM_MEMATTR_WRITE_BACK); in memory_mapping_mode()1199 return (VM_MEMATTR_WRITE_BACK); in memory_mapping_mode()1212 return (VM_MEMATTR_WRITE_BACK); in memory_mapping_mode()
673 case VM_MEMATTR_WRITE_BACK: in pmap_pte_memattr()830 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | in pmap_bootstrap_dmap()843 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L1_BLOCK); in pmap_bootstrap_dmap()869 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | in pmap_bootstrap_dmap()1050 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK; in pmap_page_init()4135 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK && in pmap_enter()4553 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK) in pmap_enter_quick_locked()5948 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK); in pmap_mapbios()6235 VM_MEMATTR_WRITE_BACK); in pmap_demote_l1()6379 VM_MEMATTR_WRITE_BACK); in pmap_demote_l2_locked()[all …]
228 mode = VM_MEMATTR_WRITE_BACK; in efi_create_1t1_map()
319 if (ma == VM_MEMATTR_WRITE_BACK && !is_cacheable_mem(pa)) in pmap_pte_cache_bits()2738 if (pmap_page_get_memattr(m) != VM_MEMATTR_WRITE_BACK) in pmap_quick_enter_page()3758 case VM_MEMATTR_WRITE_BACK:
845 MAIR_ATTR(MAIR_NORMAL_WB, VM_MEMATTR_WRITE_BACK) | in smmu_init_cd()