1 /*-
2 * Copyright (c) 2019 Emmanuel Vadot <[email protected]>
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD$
26 */
27
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/bus.h>
34
35 #include <dev/extres/clk/clk.h>
36
37 #include <arm/allwinner/clkng/aw_clk.h>
38 #include <arm/allwinner/clkng/aw_clk_mipi.h>
39
40 #include "clkdev_if.h"
41
42 /* #define dprintf(format, arg...) printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg) */
43 #define dprintf(format, arg...)
44
45 /*
46 * clknode for PLL_MIPI :
47 *
48 * clk = (pll_video0 * n * k) / m when vfb_sel=0
49 * clk depend on sint_frac, sdiv2, s6p25_7p5, pll_feedback_div when vfb_sel=1
50 *
51 */
52
53 struct aw_clk_mipi_sc {
54 uint32_t offset;
55
56 struct aw_clk_factor k;
57 struct aw_clk_factor m;
58 struct aw_clk_factor n;
59
60 uint64_t min_freq;
61 uint64_t max_freq;
62
63 uint32_t gate_shift;
64 uint32_t lock_shift;
65 uint32_t lock_retries;
66
67 uint32_t flags;
68 };
69
70 #define WRITE4(_clk, off, val) \
71 CLKDEV_WRITE_4(clknode_get_device(_clk), off, val)
72 #define READ4(_clk, off, val) \
73 CLKDEV_READ_4(clknode_get_device(_clk), off, val)
74 #define DEVICE_LOCK(_clk) \
75 CLKDEV_DEVICE_LOCK(clknode_get_device(_clk))
76 #define DEVICE_UNLOCK(_clk) \
77 CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk))
78
79 #define LDO1_EN_SHIFT 23
80 #define LDO2_EN_SHIFT 22
81 #define VFB_SEL_SHIFT 16
82
83 static int
aw_clk_mipi_init(struct clknode * clk,device_t dev)84 aw_clk_mipi_init(struct clknode *clk, device_t dev)
85 {
86 struct aw_clk_mipi_sc *sc;
87
88 sc = clknode_get_softc(clk);
89
90 clknode_init_parent_idx(clk, 0);
91 return (0);
92 }
93
94 static int
aw_clk_mipi_set_gate(struct clknode * clk,bool enable)95 aw_clk_mipi_set_gate(struct clknode *clk, bool enable)
96 {
97 struct aw_clk_mipi_sc *sc;
98 uint32_t val;
99
100 sc = clknode_get_softc(clk);
101
102 dprintf("%sabling gate\n", enable ? "En" : "Dis");
103 DEVICE_LOCK(clk);
104 READ4(clk, sc->offset, &val);
105 if (enable) {
106 val |= (1 << sc->gate_shift);
107 val |= (1 << LDO1_EN_SHIFT);
108 val |= (1 << LDO2_EN_SHIFT);
109 } else {
110 val &= ~(1 << sc->gate_shift);
111 val &= ~(1 << LDO1_EN_SHIFT);
112 val &= ~(1 << LDO2_EN_SHIFT);
113 }
114 WRITE4(clk, sc->offset, val);
115 DEVICE_UNLOCK(clk);
116
117 return (0);
118 }
119
120 static uint64_t
aw_clk_mipi_find_best(struct aw_clk_mipi_sc * sc,uint64_t fparent,uint64_t * fout,uint32_t * factor_k,uint32_t * factor_m,uint32_t * factor_n)121 aw_clk_mipi_find_best(struct aw_clk_mipi_sc *sc, uint64_t fparent, uint64_t *fout,
122 uint32_t *factor_k, uint32_t *factor_m, uint32_t *factor_n)
123 {
124 uint64_t cur, best;
125 uint32_t n, k, m;
126
127 best = 0;
128 *factor_n = 0;
129 *factor_k = 0;
130 *factor_m = 0;
131
132 for (n = aw_clk_factor_get_min(&sc->n); n <= aw_clk_factor_get_max(&sc->n); n++) {
133 for (k = aw_clk_factor_get_min(&sc->k); k <= aw_clk_factor_get_max(&sc->k); k++) {
134 for (m = aw_clk_factor_get_min(&sc->m); m <= aw_clk_factor_get_max(&sc->m); m++) {
135 cur = (fparent * n * k) / m;
136 if ((*fout - cur) < (*fout - best)) {
137 best = cur;
138 *factor_n = n;
139 *factor_k = k;
140 *factor_m = m;
141 }
142 if (best == *fout)
143 return (best);
144 }
145 }
146 }
147
148 return best;
149 }
150
151 static int
aw_clk_mipi_set_freq(struct clknode * clk,uint64_t fparent,uint64_t * fout,int flags,int * stop)152 aw_clk_mipi_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
153 int flags, int *stop)
154 {
155 struct aw_clk_mipi_sc *sc;
156 uint64_t best = 0;
157 uint32_t best_k, best_m, best_n;
158 uint32_t k, m, n;
159 uint32_t val;
160 uint32_t retry;
161
162 sc = clknode_get_softc(clk);
163
164 best = aw_clk_mipi_find_best(sc, fparent, fout, &best_k, &best_m, &best_n);
165
166 if (best < sc->min_freq ||
167 best > sc->max_freq) {
168 printf("%s: Cannot set %ju for %s (min=%ju max=%ju)\n",
169 __func__, best, clknode_get_name(clk),
170 sc->min_freq, sc->max_freq);
171 return (ERANGE);
172 }
173 if ((flags & CLK_SET_DRYRUN) != 0) {
174 *fout = best;
175 *stop = 1;
176 return (0);
177 }
178
179 DEVICE_LOCK(clk);
180 READ4(clk, sc->offset, &val);
181 /* Disable clock during freq changes */
182 val &= ~(1 << sc->gate_shift);
183 WRITE4(clk, sc->offset, val);
184
185 k = aw_clk_factor_get_value(&sc->k, best_k);
186 n = aw_clk_factor_get_value(&sc->n, best_n);
187 m = aw_clk_factor_get_value(&sc->m, best_m);
188 val &= ~sc->k.mask;
189 val &= ~sc->m.mask;
190 val &= ~sc->n.mask;
191 val |= k << sc->k.shift;
192 val |= m << sc->m.shift;
193 val |= n << sc->n.shift;
194
195 /* Write the clock changes */
196 WRITE4(clk, sc->offset, val);
197
198 /* Enable clock now that we've change it */
199 val |= 1 << sc->gate_shift;
200 WRITE4(clk, sc->offset, val);
201 DEVICE_UNLOCK(clk);
202
203 for (retry = 0; retry < sc->lock_retries; retry++) {
204 READ4(clk, sc->offset, &val);
205 if ((val & (1 << sc->lock_shift)) != 0)
206 break;
207 DELAY(1000);
208 }
209
210 *fout = best;
211 *stop = 1;
212
213 return (0);
214 }
215
216 static int
aw_clk_mipi_recalc(struct clknode * clk,uint64_t * freq)217 aw_clk_mipi_recalc(struct clknode *clk, uint64_t *freq)
218 {
219 struct aw_clk_mipi_sc *sc;
220 uint32_t val, m, n, k;
221
222 sc = clknode_get_softc(clk);
223
224 DEVICE_LOCK(clk);
225 READ4(clk, sc->offset, &val);
226 DEVICE_UNLOCK(clk);
227
228 k = aw_clk_get_factor(val, &sc->k);
229 m = aw_clk_get_factor(val, &sc->m);
230 n = aw_clk_get_factor(val, &sc->n);
231
232 *freq = (*freq * n * k) / m;
233
234 return (0);
235 }
236
237 static clknode_method_t aw_mipi_clknode_methods[] = {
238 /* Device interface */
239 CLKNODEMETHOD(clknode_init, aw_clk_mipi_init),
240 CLKNODEMETHOD(clknode_set_gate, aw_clk_mipi_set_gate),
241 CLKNODEMETHOD(clknode_recalc_freq, aw_clk_mipi_recalc),
242 CLKNODEMETHOD(clknode_set_freq, aw_clk_mipi_set_freq),
243 CLKNODEMETHOD_END
244 };
245
246 DEFINE_CLASS_1(aw_mipi_clknode, aw_mipi_clknode_class, aw_mipi_clknode_methods,
247 sizeof(struct aw_clk_mipi_sc), clknode_class);
248
249 int
aw_clk_mipi_register(struct clkdom * clkdom,struct aw_clk_mipi_def * clkdef)250 aw_clk_mipi_register(struct clkdom *clkdom, struct aw_clk_mipi_def *clkdef)
251 {
252 struct clknode *clk;
253 struct aw_clk_mipi_sc *sc;
254
255 clk = clknode_create(clkdom, &aw_mipi_clknode_class, &clkdef->clkdef);
256 if (clk == NULL)
257 return (1);
258
259 sc = clknode_get_softc(clk);
260
261 sc->offset = clkdef->offset;
262
263 sc->k.shift = clkdef->k.shift;
264 sc->k.width = clkdef->k.width;
265 sc->k.mask = ((1 << sc->k.width) - 1) << sc->k.shift;
266 sc->k.value = clkdef->k.value;
267 sc->k.flags = clkdef->k.flags;
268 sc->k.min_value = clkdef->k.min_value;
269
270 sc->m.shift = clkdef->m.shift;
271 sc->m.width = clkdef->m.width;
272 sc->m.mask = ((1 << sc->m.width) - 1) << sc->m.shift;
273 sc->m.value = clkdef->m.value;
274 sc->m.flags = clkdef->m.flags;
275 sc->m.min_value = clkdef->m.min_value;
276
277 sc->n.shift = clkdef->n.shift;
278 sc->n.width = clkdef->n.width;
279 sc->n.mask = ((1 << sc->n.width) - 1) << sc->n.shift;
280 sc->n.value = clkdef->n.value;
281 sc->n.flags = clkdef->n.flags;
282 sc->n.min_value = clkdef->n.min_value;
283
284 sc->min_freq = clkdef->min_freq;
285 sc->max_freq = clkdef->max_freq;
286
287 sc->gate_shift = clkdef->gate_shift;
288
289 sc->lock_shift = clkdef->lock_shift;
290 sc->lock_retries = clkdef->lock_retries;
291
292 sc->flags = clkdef->flags;
293
294 clknode_register(clkdom, clk);
295
296 return (0);
297 }
298