UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV (reference) in projects: f-stack

Searched refs:UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV (Results 1 – 1 of 1) sorted by relevance

/f-stack/freebsd/arm64/nvidia/tegra210/
H A D	tegra210_xusbpadctl.c	`265 #define UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(x) (((x) & 0xFF) << 20) macro 840 reg &= ~UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(~0); in uphy_sata_enable() 842 reg \|= UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(0x19); in uphy_sata_enable() 844 reg \|= UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(0x1e); in uphy_sata_enable()`