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Searched refs:UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL (Results 1 – 1 of 1) sorted by relevance

/f-stack/freebsd/arm64/nvidia/tegra210/
H A Dtegra210_xusbpadctl.c247 #define UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(x) (((x) & 0xFF) << 16) macro
579 reg &= ~UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(~0); in uphy_pex_enable()
580 reg |= UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(0x2a); in uphy_pex_enable()
802 reg &= ~UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(~0); in uphy_sata_enable()
803 reg |= UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(0x2a); in uphy_sata_enable()