Searched refs:UPHY_PLL_P0_CTL1_PLL0_FREQ_MDIV (Results 1 – 1 of 1) sorted by relevance
217 #define UPHY_PLL_P0_CTL1_PLL0_FREQ_MDIV(x) (((x) & 0x03) << 16) macro607 reg &= ~UPHY_PLL_P0_CTL1_PLL0_FREQ_MDIV(~0); in uphy_pex_enable()