1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001 - 2015 Intel Corporation
3 */
4 /*$FreeBSD$*/
5
6 #ifndef _E1000_OSDEP_H_
7 #define _E1000_OSDEP_H_
8
9 #include <stdint.h>
10 #include <stdio.h>
11 #include <stdarg.h>
12 #include <stdbool.h>
13 #include <string.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
16 #include <rte_log.h>
17 #include <rte_debug.h>
18 #include <rte_byteorder.h>
19 #include <rte_io.h>
20
21 #include "../e1000_logs.h"
22
23 #define DELAY(x) rte_delay_us_sleep(x)
24 #define usec_delay(x) DELAY(x)
25 #define usec_delay_irq(x) DELAY(x)
26 #define msec_delay(x) DELAY(1000*(x))
27 #define msec_delay_irq(x) DELAY(1000*(x))
28
29 #define DEBUGFUNC(F) DEBUGOUT(F "\n");
30 #define DEBUGOUT(S, args...) PMD_DRV_LOG_RAW(DEBUG, S, ##args)
31 #define DEBUGOUT1(S, args...) DEBUGOUT(S, ##args)
32 #define DEBUGOUT2(S, args...) DEBUGOUT(S, ##args)
33 #define DEBUGOUT3(S, args...) DEBUGOUT(S, ##args)
34 #define DEBUGOUT6(S, args...) DEBUGOUT(S, ##args)
35 #define DEBUGOUT7(S, args...) DEBUGOUT(S, ##args)
36
37 #define UNREFERENCED_PARAMETER(_p)
38 #define UNREFERENCED_1PARAMETER(_p)
39 #define UNREFERENCED_2PARAMETER(_p, _q)
40 #define UNREFERENCED_3PARAMETER(_p, _q, _r)
41 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s)
42
43 #define FALSE 0
44 #define TRUE 1
45
46 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */
47
48 /* Mutex used in the shared code */
49 #define E1000_MUTEX uintptr_t
50 #define E1000_MUTEX_INIT(mutex) (*(mutex) = 0)
51 #define E1000_MUTEX_LOCK(mutex) (*(mutex) = 1)
52 #define E1000_MUTEX_UNLOCK(mutex) (*(mutex) = 0)
53
54 typedef uint64_t u64;
55 typedef uint32_t u32;
56 typedef uint16_t u16;
57 typedef uint8_t u8;
58 typedef int64_t s64;
59 typedef int32_t s32;
60 typedef int16_t s16;
61 typedef int8_t s8;
62
63 #define __le16 u16
64 #define __le32 u32
65 #define __le64 u64
66
67 #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)
68
69 #define E1000_PCI_REG(reg) rte_read32(reg)
70
71 #define E1000_PCI_REG16(reg) rte_read16(reg)
72
73 #define E1000_PCI_REG_WRITE(reg, value) \
74 rte_write32((rte_cpu_to_le_32(value)), reg)
75
76 #define E1000_PCI_REG_WRITE_RELAXED(reg, value) \
77 rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
78
79 #define E1000_PCI_REG_WRITE16(reg, value) \
80 rte_write16((rte_cpu_to_le_16(value)), reg)
81
82 #define E1000_PCI_REG_ADDR(hw, reg) \
83 ((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))
84
85 #define E1000_PCI_REG_ARRAY_ADDR(hw, reg, index) \
86 E1000_PCI_REG_ADDR((hw), (reg) + ((index) << 2))
87
88 #define E1000_PCI_REG_FLASH_ADDR(hw, reg) \
89 ((volatile uint32_t *)((char *)(hw)->flash_address + (reg)))
90
e1000_read_addr(volatile void * addr)91 static inline uint32_t e1000_read_addr(volatile void *addr)
92 {
93 return rte_le_to_cpu_32(E1000_PCI_REG(addr));
94 }
95
e1000_read_addr16(volatile void * addr)96 static inline uint16_t e1000_read_addr16(volatile void *addr)
97 {
98 return rte_le_to_cpu_16(E1000_PCI_REG16(addr));
99 }
100
101 /* Necessary defines */
102 #define E1000_MRQC_ENABLE_MASK 0x00000007
103 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
104 #define E1000_ALL_FULL_DUPLEX ( \
105 ADVERTISE_10_FULL | ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
106
107 #define M88E1543_E_PHY_ID 0x01410EA0
108 #define ULP_SUPPORT
109
110 #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
111 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
112
113 /* Register READ/WRITE macros */
114
115 #define E1000_READ_REG(hw, reg) \
116 e1000_read_addr(E1000_PCI_REG_ADDR((hw), (reg)))
117
118 #define E1000_WRITE_REG(hw, reg, value) \
119 E1000_PCI_REG_WRITE(E1000_PCI_REG_ADDR((hw), (reg)), (value))
120
121 #define E1000_READ_REG_ARRAY(hw, reg, index) \
122 E1000_PCI_REG(E1000_PCI_REG_ARRAY_ADDR((hw), (reg), (index)))
123
124 #define E1000_WRITE_REG_ARRAY(hw, reg, index, value) \
125 E1000_PCI_REG_WRITE(E1000_PCI_REG_ARRAY_ADDR((hw), (reg), (index)), (value))
126
127 #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
128 #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
129
130 #define E1000_ACCESS_PANIC(x, hw, reg, value) \
131 rte_panic("%s:%u\t" RTE_STR(x) "(%p, 0x%x, 0x%x)", \
132 __FILE__, __LINE__, (hw), (reg), (unsigned int)(value))
133
134 /*
135 * To be able to do IO write, we need to map IO BAR
136 * (bar 2/4 depending on device).
137 * Right now mapping multiple BARs is not supported by DPDK.
138 * Fortunatelly we need it only for legacy hw support.
139 */
140
141 #define E1000_WRITE_REG_IO(hw, reg, value) \
142 E1000_WRITE_REG(hw, reg, value)
143
144 /*
145 * Tested on I217/I218 chipset.
146 */
147
148 #define E1000_READ_FLASH_REG(hw, reg) \
149 e1000_read_addr(E1000_PCI_REG_FLASH_ADDR((hw), (reg)))
150
151 #define E1000_READ_FLASH_REG16(hw, reg) \
152 e1000_read_addr16(E1000_PCI_REG_FLASH_ADDR((hw), (reg)))
153
154 #define E1000_WRITE_FLASH_REG(hw, reg, value) \
155 E1000_PCI_REG_WRITE(E1000_PCI_REG_FLASH_ADDR((hw), (reg)), (value))
156
157 #define E1000_WRITE_FLASH_REG16(hw, reg, value) \
158 E1000_PCI_REG_WRITE16(E1000_PCI_REG_FLASH_ADDR((hw), (reg)), (value))
159
160 #define STATIC static
161
162 #ifndef ETH_ADDR_LEN
163 #define ETH_ADDR_LEN 6
164 #endif
165
166 #endif /* _E1000_OSDEP_H_ */
167