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/f-stack/dpdk/drivers/net/softnic/
H A Dfirmware.cli13 pipeline TX period 10 offset_port_id 0
14 pipeline TX port in bsz 32 swq TXQ0
15 pipeline TX port out bsz 32 link LINK txq 0
16 pipeline TX table match stub
17 pipeline TX port in 0 table 0
18 pipeline TX table 0 rule add match default action fwd port 0
21 thread 1 pipeline TX enable
/f-stack/dpdk/doc/guides/platform/
H A Docteontx.rst4 OCTEON TX Board Support Package
7 This doc has information about steps to setup OCTEON TX platform
9 **Cavium OCTEON TX** SoC family.
34 OCTEON TX compatible board:
36 1. **OCTEON TX Linux kernel PF driver for Network acceleration HW blocks**
67 Setup Platform Using OCTEON TX SDK
70 The OCTEON TX platform drivers can be compiled either natively on
71 **OCTEON TX** :sup:`®` board or cross-compiled on an x86 based platform.
74 OCTEON TX SDK 6.2.0 patch 3. In this, the PF drivers for all hardware
92 Once the target is ready for native compilation, the OCTEON TX platform
[all …]
/f-stack/dpdk/doc/guides/nics/
H A Dsoftnic.rst151 pipeline TX table match stub
152 pipeline TX port in 0 table 0
155 thread 2 pipeline TX enable
178 TX queue: 0
179 TX desc=512 - TX free threshold=32
181 TX offloads=0x0 - TX RS bit threshold=32
188 TX queue: 0
189 TX desc=0 - TX free threshold=0
191 TX offloads=0x0 - TX RS bit threshold=0
356 pipeline TX port in 0 table 0
[all …]
H A Dkni.rst132 TX packets 0 bytes 0 (0.0 B)
133 TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
139 TX packets 0 bytes 0 (0.0 B)
140 TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
159 TX-packets: 35637947 TX-dropped: 0 TX-total: 35637947
164 TX-packets: 35637937 TX-dropped: 0 TX-total: 35637937
169 TX-packets: 71275884 TX-dropped: 0 TX-total: 71275884
H A Docteontx.rst4 OCTEON TX Poll Mode driver
7 The OCTEON TX ETHDEV PMD (**librte_net_octeontx**) provides poll mode ethdev
8 driver support for the inbuilt network device found in the **Cavium OCTEON TX**
17 Features of the OCTEON TX Ethdev PMD are:
28 - Multiple queues for TX
32 Supported OCTEON TX SoCs
43 - Scattered and gather for TX and RX
111 The OCTEON TX ethdev pmd is exposed as a vdev device which consists of a set
145 The OCTEON TX SoC family NIC has inbuilt HW assisted external mempool manager.
148 recycling on OCTEON TX SoC platform.
[all …]
H A Dfm10k.rst23 appropriate FTAG is inserted for every frame on TX side.
34 There is no change to the PMD API. The RX/TX handlers are the only two entries for
35 vPMD packet I/O. They are transparently registered at runtime RX/TX execution
39 packet transfers. The following sections explain RX and TX constraints in the
99 TX Constraint
102 Features not Supported by TX Vector PMD
105 TX vPMD only works when offloads is set to 0
107 This means that it does not support any TX offload.
H A Dszedata2.rst128 PMD: Available DMA channels RX: 8 TX: 8
143 TX queues=2 - TX desc=512 - TX free threshold=0
144 TX threshold registers: pthresh=0 hthresh=0 wthresh=0
145 TX RS bit threshold=0 - TXQ flags=0x0
/f-stack/freebsd/contrib/device-tree/Bindings/display/bridge/
H A Drenesas,dw-hdmi.txt1 Renesas Gen3 DWC HDMI TX Encoder
4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
15 - "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX
16 - "renesas,r8a774b1-hdmi" for R8A774B1 (RZ/G2N) compatible HDMI TX
17 - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
18 - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
19 - "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
21 HDMI TX
H A Ddw_hdmi.txt1 Synopsys DesignWare HDMI TX Encoder
5 TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
13 - reg: Memory mapped base address and length of the DWC HDMI TX registers.
19 - interrupts: Reference to the DWC HDMI TX interrupt.
24 - clock-names: The DWC HDMI TX uses the following clocks.
30 - ports: The connectivity of the DWC HDMI TX with the rest of the system is
/f-stack/freebsd/contrib/device-tree/Bindings/net/
H A Dmicrel-ksz90x1.txt51 - txen-skew-ps : Skew control of TX CTL pad
56 - txd0-skew-ps : Skew control of TX data 0 pad
57 - txd1-skew-ps : Skew control of TX data 1 pad
58 - txd2-skew-ps : Skew control of TX data 2 pad
59 - txd3-skew-ps : Skew control of TX data 3 pad
73 - txc-skew-ps : Skew control of TX clock pad
78 - txen-skew-ps : Skew control of TX CTL pad
83 - txd0-skew-ps : Skew control of TX data 0 pad
84 - txd1-skew-ps : Skew control of TX data 1 pad
85 - txd2-skew-ps : Skew control of TX data 2 pad
[all …]
H A Dxilinx_axienet.txt7 segments of memory for buffering TX and RX, as well as the capability of
8 offloading TX/RX checksum calculation off the processor.
24 - interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
26 specified, the TX/RX DMA interrupts should be on that node
37 - xlnx,txcsum : 0 or empty for disabling TX checksum offload,
38 1 to enable partial TX checksum offload,
39 2 to enable full TX checksum offload
49 device (DMA registers and DMA TX/RX interrupts) rather
H A Dlantiq,xrx200-net.txt9 - interrupts : TX and RX DMA interrupts. Use interrupt-names "tx" for
10 : the TX interrupt and "rx" for the RX interrupt.
/f-stack/dpdk/doc/guides/cryptodevs/
H A Docteontx.rst4 Cavium OCTEON TX Crypto Poll Mode Driver
7 The OCTEON TX crypto poll mode driver provides support for offloading
9 **OCTEON TX** :sup:`®` family of processors (CN8XXX). The OCTEON TX crypto
66 The OCTEON TX crypto poll mode driver can be compiled either natively on
67 **OCTEON TX** :sup:`®` board or cross-compiled on an x86 based platform.
74 OCTEON TX crypto PF driver needs microcode to be available at `/lib/firmware/` directory.
90 by using dpdk-devbind.py script. The OCTEON TX crypto PF device need to be
115 OCTEON TX crypto PMD.
125 The symmetric crypto operations on OCTEON TX crypto PMD may be verified by running the test
133 The asymmetric crypto operations on OCTEON TX crypto PMD may be verified by running the test
/f-stack/dpdk/doc/guides/compressdevs/
H A Docteontx.rst4 OCTEON TX ZIP Compression Poll Mode Driver
7 The OCTEON TX ZIP PMD (**librte_compress_octeontx**) provides poll mode
9 **Cavium OCTEON TX** SoC family.
17 OCTEON TX ZIP PMD has support for:
37 Supported OCTEON TX SoCs
45 OCTEON TX SDK includes kernel image which provides OCTEON TX ZIP PF
54 For more information on building and booting linux kernel on OCTEON TX
62 The OCTEON TX zip is exposed as pci device which consists of a set of
/f-stack/dpdk/doc/guides/mempool/
H A Docteontx.rst4 OCTEON TX FPAVF Mempool Driver
7 The OCTEON TX FPAVF PMD (**librte_mempool_octeontx**) is a mempool
8 driver for offload mempool device found in **Cavium OCTEON TX** SoC
17 Features of the OCTEON TX FPAVF PMD are:
23 Supported OCTEON TX SoCs
55 The OCTEON TX fpavf mempool initialization similar to other mempool
/f-stack/dpdk/doc/guides/sample_app_ug/
H A Deventdev_pipeline.rst38 * ``-t1``: core mask 0x1 for TX
121 worker 12 thread done. RX=4966581 TX=4966581
122 worker 13 thread done. RX=4963329 TX=4963329
123 worker 14 thread done. RX=4953614 TX=4953614
124 worker 0 thread done. RX=0 TX=0
125 worker 11 thread done. RX=4970549 TX=4970549
126 worker 10 thread done. RX=4986391 TX=4986391
127 worker 9 thread done. RX=4970528 TX=4970528
128 worker 15 thread done. RX=4974087 TX=4974087
129 worker 8 thread done. RX=4979908 TX=4979908
[all …]
H A Dqos_scheduler.rst27 If a separate TX core is used, these are sent to the TX ring.
28 Otherwise, they are sent directly to the TX port.
29 The TX thread, if present, reads from the TX ring and write the packets to the TX port.
64 * --pfc "RX PORT, TX PORT, RX LCORE, WT LCORE, TX CORE": Packet flow configuration.
66 having 4 or 5 items (if TX core defined or not).
84 * C = Size (in number of buffer descriptors) of each of the NIC TX rings written
96 * D = Worker lcore write burst size to the NIC TX (the default value is 64)
108 * --tth "A, B, C": TX queue threshold parameters
110 * A = TX prefetch threshold (the default value is 36)
112 * B = TX host threshold (the default value is 0)
[all …]
H A Drxtx_callbacks.rst4 RX/TX Callbacks Sample Application
7 The RX/TX Callbacks sample application is a packet forwarding application that
53 The sections below explain the additional RX/TX callback code.
99 /* Allocate and set up 1 TX queue per Ethernet port. */
117 /* Add the callbacks for RX and TX.*/
125 The RX and TX callbacks are added to the ports/queues as function pointers:
168 The ``calc_latency()`` callback is added to the TX port and is applied to all
/f-stack/dpdk/doc/guides/eventdevs/
H A Docteontx.rst4 OCTEON TX SSOVF Eventdev Driver
7 The OCTEON TX SSOVF PMD (**librte_event_octeontx**) provides poll mode
8 eventdev driver support for the inbuilt event device found in the **Cavium OCTEON TX**
17 Features of the OCTEON TX SSOVF PMD are:
35 Supported OCTEON TX SoCs
48 The OCTEON TX eventdev is exposed as a vdev device which consists of a set
110 Max number of events in OCTEON TX Eventdev (SSO) are only limited by DRAM size
/f-stack/freebsd/contrib/device-tree/Bindings/dma/
H A Dste-dma40.txt60 bidirectional, i.e. the same for RX and TX operations:
111 49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
112 50: Hash Accelerator 1 TX
113 51: memcpy TX (to be used by the DMA driver for memcpy operations)
124 62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
125 63: Hash Accelerator 0 TX
/f-stack/freebsd/contrib/device-tree/Bindings/sound/
H A Dnvidia,tegra30-ahub.txt61 For TX CIFs, the numbers indicate the bit position within the AHUB routing
62 registers (APBIF 0..3 TX, I2S 0..5 TX, DAM 0..2 TX, SPDIF TX 0..1).
/f-stack/dpdk/doc/guides/testpmd_app_ug/
H A Drun_app.rst89 Enable NUMA-aware allocation of RX/TX rings and of RX memory buffers
103 Where flag is 1 for RX, 2 for TX, and 3 for RX and TX.
276 Set the number of TX queues per port to N, where 1 <= N <= 65535.
281 Set the number of descriptors in the TX rings to N, where N > 0.
288 number of TX queues and to the number of RX queues. then the first
290 binded to the second TX hairpin and so on. The index of the first
292 The index of the first TX hairpin queue is the number of TX queues
334 Set the host threshold register of TX rings to N, where N >= 0.
358 Set the TX queues statistics counters mapping 0 <= mapping <= 15.
430 Set the hexadecimal bitmask of TX queue offloads.
[all …]
/f-stack/freebsd/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-gxbb-nanopi-k2.dts197 gpio-line-names = "UART TX", "UART RX", "Power Control", "Power Key In",
210 "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
211 "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3",
246 "Bluetooth UART TX", "Bluetooth UART RX",
/f-stack/freebsd/contrib/device-tree/Bindings/media/i2c/
H A Dtc358743.txt1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
/f-stack/freebsd/contrib/device-tree/Bindings/display/imx/
H A Dhdmi.txt1 Freescale i.MX6 DWC HDMI TX Encoder
4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in

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