Searched refs:TEGRA210_CLK_PLL_C4_OUT0 (Results 1 – 4 of 4) sorted by relevance
342 #define TEGRA210_CLK_PLL_C4_OUT0 308 macro
145 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;1215 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,1217 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;1281 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;1282 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
333 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
561 DIV_TB(TEGRA210_CLK_PLL_C4_OUT0,