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Searched refs:SRBC_UHC_SR (Results 1 – 2 of 2) sorted by relevance

/f-stack/freebsd/mips/ingenic/
H A Djz4780_clock.c752 reg |= SRBC_UHC_SR; in jz4780_ehci_enable()
758 reg &= ~(SRBC_UHC_SR); in jz4780_ehci_enable()
H A Djz4780_regs.h340 #define SRBC_UHC_SR 0x00004000 /* UHC soft reset*/ macro