| /f-stack/freebsd/contrib/device-tree/Bindings/spi/ |
| H A D | spi-sprd.txt | 1 Spreadtrum SPI Controller
5 - reg: Offset and length of SPI controller register space.
6 - interrupts: Should contain SPI interrupt.
8 "spi" for SPI clock,
9 "source" for SPI source (parent) clock,
10 "enable" for SPI module enable clock.
14 address on the SPI bus. Should be set to 1.
18 dma-names: Should contain names of the SPI used DMA channel.
19 dmas: Should contain DMA channels and DMA slave ids which the SPI used
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| H A D | qcom,spi-geni-qcom.txt | 1 GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
4 (an output FIFO and an input FIFO) for serial peripheral interface (SPI)
7 SPI in master mode supports up to 50MHz, up to four chip selects, programmable
12 - reg: Must contain SPI register location and length.
13 - interrupts: Must contain SPI controller interrupts.
17 the SPI bus.
20 SPI Controller nodes must be child of GENI based Qualcomm Universal
24 SPI slave nodes must be children of the SPI master node and conform to SPI bus
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| H A D | spi-davinci.txt | 1 Davinci SPI controller device bindings
10 address on the SPI bus. Should be set to 1.
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
20 - ti,davinci-spi-intr-line: interrupt line used to connect the SPI
35 and an args specifier containing the SPI device id
45 SPI slave nodes can contain the following properties.
46 Not all SPI Peripherals from Texas Instruments support this.
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| H A D | spi-controller.yaml | 7 title: SPI Controller Generic Binding
13 SPI busses can be described with a node for the SPI controller device
14 and a set of child nodes for each SPI slave on the bus. The system SPI
15 controller may be described for use in SPI master mode or in SPI slave mode,
53 The SPI controller acts as a slave, instead of a master.
68 Compatible of the SPI device.
79 Compatible of the SPI device.
115 Maximum SPI clocking speed of the device in Hz.
119 Bus width to the SPI bus used for read transfers.
130 Bus width to the SPI bus used for write transfers.
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| H A D | spi-bcm63xx-hsspi.txt | 1 Binding for Broadcom BCM6328 High Speed SPI controller
6 - interrupts: Interrupt for the SPI block.
7 - clocks: phandles of the SPI clock and the PLL clock.
9 - #address-cells: <1>, as required by generic SPI binding.
10 - #size-cells: <0>, also as required by generic SPI binding.
16 Child nodes as per the generic SPI binding.
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| H A D | spi-bcm63xx.txt | 1 Binding for Broadcom BCM6348/BCM6358 SPI controller
6 - interrupts: Interrupt for the SPI block.
7 - clocks: phandle of the SPI clock.
9 - #address-cells: <1>, as required by generic SPI binding.
10 - #size-cells: <0>, also as required by generic SPI binding.
16 Child nodes as per the generic SPI binding.
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| H A D | fsl-imx-cspi.txt | 6 - "fsl,imx1-cspi" for SPI compatible with the one integrated on i.MX1
7 - "fsl,imx21-cspi" for SPI compatible with the one integrated on i.MX21
8 - "fsl,imx27-cspi" for SPI compatible with the one integrated on i.MX27
9 - "fsl,imx31-cspi" for SPI compatible with the one integrated on i.MX31
10 - "fsl,imx35-cspi" for SPI compatible with the one integrated on i.MX35
11 - "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51
12 - "fsl,imx53-ecspi" for SPI compatible with the one integrated on i.MX53 and later Soc
13 - "fsl,imx8mq-ecspi" for SPI compatible with the one integrated on i.MX8MQ
14 - "fsl,imx8mm-ecspi" for SPI compatible with the one integrated on i.MX8MM
15 - "fsl,imx8mn-ecspi" for SPI compatible with the one integrated on i.MX8MN
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| H A D | nvidia,tegra114-spi.txt | 1 NVIDIA Tegra114 SPI controller.
7 - reg: Should contain SPI registers location and length.
8 - interrupts: Should contain SPI interrupts.
29 Tegra SPI master with respect to outgoing Tegra SPI master clock.
30 Tap values vary based on the platform design trace lengths from Tegra SPI
33 with this tap value. This property is used to adjust the Tegra SPI master
34 clock with respect to the data from the SPI slave device.
35 Tap values vary based on the platform design trace lengths from Tegra SPI
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| H A D | adi,axi-spi-engine.txt | 1 Analog Devices AXI SPI Engine controller Device Tree Bindings
15 Subnodes are use to represent the SPI slave devices connected to the SPI
16 master. They follow the generic SPI bindings as outlined in spi-bus.txt.
30 /* SPI devices */
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| H A D | qcom,spi-qup.txt | 1 Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
4 and an input FIFO) for serial peripheral interface (SPI) mini-core.
6 SPI in master mode supports up to 50MHz, up to four chip selects, programmable
23 address on the SPI bus. Should be set to 1.
27 - spi-max-frequency: Specifies maximum SPI clock frequency,
32 The gpios will be referred to as reg = <index> in the SPI child
33 nodes. If unspecified, a single SPI device without a chip
42 SPI slave nodes must be children of the SPI master node and can contain
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| H A D | spi-xlp.txt | 1 SPI Master controller for Netlogic XLP MIPS64 SOCs
4 Currently this SPI controller driver is supported for the following
11 on the SPI bus.
17 SPI slave nodes must be children of the SPI master node and can contain
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| H A D | snps,dw-apb-ssi.yaml | 29 - description: Generic DW SPI Controller
33 - description: Microsemi Ocelot/Jaguar2 SoC SPI Controller
39 - description: Amazon Alpine SPI Controller
41 - description: Renesas RZ/N1 SPI Controller
45 - description: Intel Keem Bay SPI Controller
52 - description: SPI MST region map
60 - description: SPI Controller reference clock source
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| H A D | spi-mux.yaml | 7 title: Generic SPI Multiplexer
10 This binding describes a SPI bus multiplexer to route the SPI chip select
11 signals. This can be used when you need more devices than the SPI controller
13 setting of the multiplexer to a channel needs to be done by a specific SPI mux
24 | | SPI +-|-------+ Mux |\\ CS-0 | | | |
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| H A D | spi-octeon.txt | 1 Cavium, Inc. OCTEON SOC SPI master controller.
7 - #address-cells : <1>, as required by generic SPI binding.
8 - #size-cells : <0>, also as required by generic SPI binding.
10 Child nodes as per the generic SPI binding.
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| H A D | spi-ath79.txt | 1 Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller
8 - #address-cells: <1>, as required by generic SPI binding.
9 - #size-cells: <0>, also as required by generic SPI binding.
11 Child nodes as per the generic SPI binding.
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| H A D | spi-orion.txt | 1 Marvell Orion SPI device
13 the SPI direct access mode that some of the Marvell SoCs support
20 - cell-index : Which of multiple SPI controllers is this.
43 Example with SPI direct mode support (optionally):
62 'soc' node needs to add the entries for the desired SPI controllers
64 mode. Here an example for this (SPI controller 0, device 1 and SPI
65 controller 1, device 2 are used in direct mode. All other SPI device
69 * Enable the SPI direct access by configuring an entry
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| H A D | brcm,spi-bcm-qspi.txt | 1 Broadcom SPI controller
3 The Broadcom SPI controller is a SPI master found on various SOCs, including
4 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits
6 MSPI : SPI master controller can read and write to a SPI slave device
7 BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration
14 use SPI protocol.
19 Must be <1>, as required by generic SPI binding.
22 Must be <0>, also as required by generic SPI binding.
61 - "mspi_done": Indicates that the requested SPI operation is complete.
84 SPI Master (MSPI+BSPI) for SPI-NOR access:
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| /f-stack/freebsd/contrib/device-tree/Bindings/net/ |
| H A D | qca,qca7000.txt | 4 be configured either as SPI or UART slave. This configuration is done by
7 (a) Ethernet over SPI
9 In order to use the QCA7000 as SPI device it must be defined as a child of a
10 SPI master in the device tree.
14 - reg : Should specify the SPI chip select
24 are invalid. Missing the property will set the SPI
27 In this mode the SPI master must toggle the chip select
36 SPI Example:
38 /* Freescale i.MX28 SPI master*/
51 spi-cpha; /* SPI mode: CPHA=1 */
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| /f-stack/freebsd/contrib/device-tree/Bindings/mtd/ |
| H A D | aspeed-smc.txt | 2 * Aspeed SPI Flash Memory Controller
5 three chip selects, two of which are always of SPI type and the third
6 can be SPI or NOR type flash. These bindings only describe SPI.
8 The two SPI flash memory controllers in the AST2500 each support two
14 "aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller
16 "aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers
27 The child nodes are the SPI flash modules which must have a compatible
30 Optionally, the child node can contain properties for SPI mode (may be
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| /f-stack/freebsd/contrib/device-tree/Bindings/net/nfc/ |
| H A D | st95hf.txt | 3 ST NFC Transceiver is required to attach with SPI bus.
4 ST95HF node should be defined in DT as SPI slave device of SPI
11 - reg: Address of SPI slave "ST95HF transceiver" on SPI master bus.
15 - spi-max-frequency: Max. operating SPI frequency for ST95HF
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| /f-stack/freebsd/contrib/device-tree/Bindings/misc/ |
| H A D | lwn-bk4.txt | 1 * Liebherr's BK4 controller external SPI
5 The SPI is used for data and management purposes in both master and
12 Required SPI properties:
17 - spi-max-frequency : Maximum SPI clocking speed of device in Hz, should be
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| /f-stack/freebsd/contrib/device-tree/Bindings/pinctrl/ |
| H A D | pinctrl-mcp23s08.txt | 2 8-/16-bit I/O expander with serial interface (I2C/SPI)
6 - "mcp,mcp23s08" (DEPRECATED) for 8 GPIO SPI version
7 - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version
11 - "microchip,mcp23s08" for 8 GPIO SPI version
12 - "microchip,mcp23s17" for 16 GPIO SPI version
13 - "microchip,mcp23s18" for 16 GPIO SPI version
26 SPI uses this to specify the chipselect line which the chip is
27 connected to. The driver and the SPI variant of the chip support
31 Required device specific properties (only for SPI chips):
40 least one bit to 1 for SPI chips.
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| /f-stack/freebsd/contrib/device-tree/Bindings/net/wireless/ |
| H A D | ti,wl1251.txt | 3 The wl1251 chip can be connected via SPI or via SDIO. This
4 document describes the binding for the SPI connected chip.
9 - spi-max-frequency : Maximum SPI clocking speed of device in Hz
17 SPI mode
19 for optional SPI connection related properties,
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| /f-stack/freebsd/contrib/device-tree/Bindings/rtc/ |
| H A D | epson,rx6110.txt | 4 The Epson RX6110 can be used with SPI or I2C busses. The kind of
21 SPI mode
28 - spi-cpha: RX6110 works with SPI shifted clock phase
29 - spi-cpol: RX6110 works with SPI inverse clock polarity
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| /f-stack/freebsd/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | marvell,gicp.txt | 4 GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
7 into GIC SPI interrupts.
13 - reg: Must be the address and size of the GICP SPI registers
15 - marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
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