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Searched refs:SM (Results 1 – 22 of 22) sorted by relevance

/f-stack/freebsd/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_aic.c528 SM(37, AR_PHY_AIC_F_WLAN) | in ar9300_aic_calibration()
532 SM(0, AR_PHY_AIC_ENABLE))); in ar9300_aic_calibration()
539 SM(0, AR_PHY_AIC_ENABLE))); in ar9300_aic_calibration()
549 SM(15, AR_PHY_AIC_RSSI_MAX) | in ar9300_aic_calibration()
550 SM(0, AR_PHY_AIC_RSSI_MIN))); in ar9300_aic_calibration()
555 SM(15, AR_PHY_AIC_RSSI_MAX) | in ar9300_aic_calibration()
556 SM(0, AR_PHY_AIC_RSSI_MIN))); in ar9300_aic_calibration()
707 SM(15, AR_PHY_AIC_RSSI_MAX) | in ar9300_aic_start_normal()
708 SM(0, AR_PHY_AIC_RSSI_MIN))); in ar9300_aic_start_normal()
711 (SM(15, AR_PHY_AIC_RSSI_MAX) | in ar9300_aic_start_normal()
[all …]
H A Dar9300_radar.c243 val |= SM(pe->pe_enabled, AR_PHY_RADAR_0_ENA);
248 val |= SM(pe->pe_firpwr, AR_PHY_RADAR_0_FIRPWR);
252 val |= SM(pe->pe_rrssi, AR_PHY_RADAR_0_RRSSI);
256 val |= SM(pe->pe_height, AR_PHY_RADAR_0_HEIGHT);
269 val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI);
274 val |= SM(pe->pe_inband, AR_PHY_RADAR_0_INBAND);
282 val |= SM(pe->pe_maxlen, AR_PHY_RADAR_1_MAXLEN);
471 SM(qi->tqi_cwmin, AR_D_LCL_IFS_CWMIN)
472 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
473 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
[all …]
H A Dar9300_xmit.c328 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) in ar9300_reset_tx_queue()
329 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); in ar9300_reset_tx_queue()
334 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) | in ar9300_reset_tx_queue()
335 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) | in ar9300_reset_tx_queue()
336 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)); in ar9300_reset_tx_queue()
355 SM(qi->tqi_cbrOverflowLimit, in ar9300_reset_tx_queue()
395 dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, in ar9300_reset_tx_queue()
401 dmisc |= SM(AR_D_MISC_VIR_COL_HANDLING_IGNORE, in ar9300_reset_tx_queue()
419 | SM(0, AR_D_LCL_IFS_CWMAX) in ar9300_reset_tx_queue()
459 dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, in ar9300_reset_tx_queue()
[all …]
H A Dar9300_mci.c938 SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) | in ar9300_mci_set_btcoex_ctrl_9565_1ANT()
939 SM(1, AR_BTCOEX_CTRL_PA_SHARED) | in ar9300_mci_set_btcoex_ctrl_9565_1ANT()
940 SM(1, AR_BTCOEX_CTRL_LNA_SHARED) | in ar9300_mci_set_btcoex_ctrl_9565_1ANT()
943 SM(0, AR_BTCOEX_CTRL_1_CHAIN_ACK) | in ar9300_mci_set_btcoex_ctrl_9565_1ANT()
944 SM(0, AR_BTCOEX_CTRL_1_CHAIN_BCN) | in ar9300_mci_set_btcoex_ctrl_9565_1ANT()
958 SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) | in ar9300_mci_set_btcoex_ctrl_9565_2ANT()
959 SM(0, AR_BTCOEX_CTRL_PA_SHARED) | in ar9300_mci_set_btcoex_ctrl_9565_2ANT()
960 SM(0, AR_BTCOEX_CTRL_LNA_SHARED) | in ar9300_mci_set_btcoex_ctrl_9565_2ANT()
978 SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) | in ar9300_mci_set_btcoex_ctrl_9462()
979 SM(1, AR_BTCOEX_CTRL_PA_SHARED) | in ar9300_mci_set_btcoex_ctrl_9462()
[all …]
H A Dar9300_timer.c148 (SM(AR_GENTMR_BIT(index), AR_IMR_S5_GENTIMER_THRESH) | in ar9300_start_generic_timer()
149 SM(AR_GENTMR_BIT(index), AR_IMR_S5_GENTIMER_TRIG))); in ar9300_start_generic_timer()
168 (SM(AR_GENTMR_BIT(index), AR_IMR_S5_GENTIMER_THRESH) | in ar9300_stop_generic_timer()
169 SM(AR_GENTMR_BIT(index), AR_IMR_S5_GENTIMER_TRIG))); in ar9300_stop_generic_timer()
H A Dar9300_xmit_ds.c114 ads->ds_ctl17 = __bswap32(SM(key_type, AR_encr_type)); in ar9300_fill_tx_desc()
118 ads->ds_ctl17 = SM(key_type, AR_encr_type); in ar9300_fill_tx_desc()
128 ads->ds_ctl17 = SM(key_type, AR_encr_type); in ar9300_fill_tx_desc()
574 ads->ds_ctl12 |= SM((1 << chain_num), AR_paprd_chain_mask); in ar9300_set_paprd_tx_desc()
614 | SM(tx_power, AR_xmit_power0) in ar9300_set_11n_tx_desc()
622 | SM(type, AR_frame_type) in ar9300_set_11n_tx_desc()
770 | SM(0, AR_burst_dur); in ar9300_set_11n_rate_scenario()
868 ads->ds_ctl17 |= SM(aggr_len, AR_aggr_len); in ar9300_set_11n_aggr_first()
869 ads->ds_ctl17 |= SM(num_delims, AR_pad_delim); in ar9300_set_11n_aggr_first()
887 ctl17 |= SM(num_delims, AR_pad_delim); in ar9300_set_11n_aggr_middle()
[all …]
H A Dar9300_spectral.c82 val |= SM(MAX_RADAR_RSSI_THRESH, AR_PHY_RADAR_0_RRSSI); in ar9300_disable_radar()
85 val |= SM(MAX_RADAR_HEIGHT, AR_PHY_RADAR_0_HEIGHT); in ar9300_disable_radar()
114 val |= SM(MAX_RADAR_DC_PWR_THRESH, AR_PHY_RADAR_DC_PWR_THRESH); in ar9300_set_radar_dc_thresh()
352 val |= SM(ss->ss_fft_period, AR_PHY_SPECTRAL_SCAN_FFT_PERIOD); in ar9300_configure_spectral_scan()
357 val |= SM(ss->ss_period, AR_PHY_SPECTRAL_SCAN_PERIOD); in ar9300_configure_spectral_scan()
367 val |= SM(0, AR_PHY_SPECTRAL_SCAN_COUNT); in ar9300_configure_spectral_scan()
369 val |= SM(ss->ss_count, AR_PHY_SPECTRAL_SCAN_COUNT); in ar9300_configure_spectral_scan()
375 val |= SM(ss->ss_period, AR_PHY_SPECTRAL_SCAN_PERIOD); in ar9300_configure_spectral_scan()
H A Dar9300_misc.c2402 SM(btconf->bt_time_extend, AR_BT_TIME_EXTEND) | in ar9300_bt_coex_config()
2405 SM(btconf->bt_mode, AR_BT_MODE) | in ar9300_bt_coex_config()
2406 SM(btconf->bt_quiet_collision, AR_BT_QUIET) | in ar9300_bt_coex_config()
2426 ahp->ah_bt_coex_mode |= SM(qnum, AR_BT_QCU_THRESH); in ar9300_bt_coex_set_qcu_thresh()
3006 SM(WB225_OB_GREEN_TX_SHORT_VALUE, in ar9300_chk_rssi_update_tx_pwr()
3008 SM(WB225_OB_GREEN_TX_SHORT_VALUE, in ar9300_chk_rssi_update_tx_pwr()
3010 SM(WB225_OB_GREEN_TX_SHORT_VALUE, in ar9300_chk_rssi_update_tx_pwr()
3013 temp_tcp_reg_val = (SM(6, AR_TPC_ACK) | in ar9300_chk_rssi_update_tx_pwr()
3037 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, in ar9300_chk_rssi_update_tx_pwr()
3039 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, in ar9300_chk_rssi_update_tx_pwr()
[all …]
H A Dar9300desc.h445 (SM((_series)[_index].Tries, AR_xmit_data_tries##_index))
448 (SM((_series)[_index].Rate, AR_xmit_rate##_index))
451 (SM((_series)[_index].PktDuration, AR_packet_dur##_index) |\
467 |SM((_series)[_index].ChSel, AR_chain_sel##_index)
470 SM(_txpower, AR_xmit_power##_index)
H A Dar9300_beacon.c170 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) in ar9300_set_sta_beacon_timers()
187 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); in ar9300_set_sta_beacon_timers()
H A Dar9300_reset.c143 usec = SM(AR_USEC_HALF_FAST_CLOCK, AR_USEC_USEC); in ar9300_set_ifs_timing()
147 usec = SM(AR_USEC_HALF, AR_USEC_USEC); in ar9300_set_ifs_timing()
159 usec = SM(AR_USEC_QUARTER, AR_USEC_USEC); in ar9300_set_ifs_timing()
1630 pll = SM(0x5, AR_RTC_PLL_REFDIV); in ar9300_init_pll()
1635 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); in ar9300_init_pll()
1637 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); in ar9300_init_pll()
1641 pll |= SM(0x28, AR_RTC_PLL_DIV); in ar9300_init_pll()
1649 pll |= SM(0x2c, AR_RTC_PLL_DIV); in ar9300_init_pll()
4263 SM(2, AR_QOS_NO_ACK_TWO_BIT) | in ar9300_init_qos()
4264 SM(5, AR_QOS_NO_ACK_BIT_OFF) | in ar9300_init_qos()
[all …]
H A Dar9300_interrupts.c676 mask |= SM(ahp->ah_gpio_mask, AR_INTR_ASYNC_MASK_GPIO);
712 mask |= SM(ahp->ah_gpio_mask, AR_INTR_SYNC_MASK_GPIO);
H A Dar9300_eeprom.c951 tpc_reg_val = (SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], AR_TPC_ACK) | in ar9300_selfgen_tpc_reg_write()
952 SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], AR_TPC_CTS) | in ar9300_selfgen_tpc_reg_write()
953 SM(0x3f, AR_TPC_CHIRP) | in ar9300_selfgen_tpc_reg_write()
954 SM(0x3f, AR_TPC_RPT)); in ar9300_selfgen_tpc_reg_write()
956 tpc_reg_val = (SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], AR_TPC_ACK) | in ar9300_selfgen_tpc_reg_write()
957 SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], AR_TPC_CTS) | in ar9300_selfgen_tpc_reg_write()
958 SM(0x3f, AR_TPC_CHIRP) | in ar9300_selfgen_tpc_reg_write()
959 SM(0x3f, AR_TPC_RPT)); in ar9300_selfgen_tpc_reg_write()
H A Dar9300_keycache.c268 uapsd_cfg = (u_int32_t) SM(uapsd_cfg, AR_KEYTABLE_UAPSD); in ar9300_set_key_cache_entry()
H A Dar9300_power.c771 regval = SM(AR_PCU_SMPS_LPWR_CHNMSK_VAL, AR_PCU_SMPS_LPWR_CHNMSK) | in ar9300_set_sm_power_mode()
772 SM(ahp->ah_rx_chainmask, AR_PCU_SMPS_HPWR_CHNMSK) | in ar9300_set_sm_power_mode()
/f-stack/freebsd/arm64/nvidia/tegra210/
H A Dtegra210_clk_super.c52 #define SM(_id, cn, pl, r) \ macro
83 SM(TEGRA210_CLK_CCLK_G, "cclk_g", cclk_g_parents, CCLKG_BURST_POLICY),
84 SM(TEGRA210_CLK_CCLK_LP, "cclk_lp", cclk_lp_parents, CCLKLP_BURST_POLICY),
85 SM(TEGRA210_CLK_SCLK, "sclk", sclk_parents, SCLK_BURST_POLICY),
/f-stack/freebsd/arm/nvidia/tegra124/
H A Dtegra124_clk_super.c56 #define SM(_id, cn, pl, r, x, d, f) \ macro
90 SM(TEGRA124_CLK_CCLK_G, "cclk_g", cclk_g_parents, CCLKG_BURST_POLICY, 0, 0, 0),
91 …SM(TEGRA124_CLK_CCLK_LP, "cclk_lp", cclk_lp_parents, CCLKLP_BURST_POLICY, 8, 16, SMF_HAVE_DIVIDER_…
92 SM(TEGRA124_CLK_SCLK, "sclk", sclk_parents, SCLK_BURST_POLICY, 0, 0, 0),
/f-stack/freebsd/contrib/device-tree/Bindings/display/
H A Dsm501fb.txt1 * SM SM501
3 The SM SM501 is a LCD controller, with proper hardware, it can also
/f-stack/freebsd/contrib/device-tree/Bindings/arm/
H A Drenesas.yaml101 - iwave,g22m # iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM)
/f-stack/freebsd/contrib/device-tree/src/arm/
H A Dste-snowball.dts476 * Mux in "SM" which is used for the
H A Dam335x-osd3358-sm-red.dts18 model = "Octavo Systems OSD3358-SM-RED";
/f-stack/app/redis-5.0.5/deps/jemalloc/build-aux/
H A Dconfig.guess1204 SM[BE]S:UNIX_SV:*:*)