Searched refs:SEC (Results 1 – 18 of 18) sorted by relevance
1 Freescale SoC SEC Security Engines versions 1.x-2.x-3.x10 - interrupts : the SEC's interrupt number21 bit 1 = set if SEC has the ARC4 EU (AFEU)22 bit 2 = set if SEC has the DES/3DES EU (DEU)23 bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)25 bit 5 = set if SEC has the public key EU (PKEU)26 bit 6 = set if SEC has the AES EU (AESU)27 bit 7 = set if SEC has the Kasumi EU (KEU)28 bit 8 = set if SEC has the CRC EU (CRCU)31 remaining bits are reserved for future SEC EUs.[all …]
1 SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).2 Currently Freescale powerpc chip C29X is embedded with SEC 6.3 SEC 6 device tree binding include:4 -SEC 6 Node9 SEC 6 Node13 Node defines the base address of the SEC 6 block.15 configuration registers for the SEC 6 block.16 For example, In C293, we could see three SEC 6 node.28 Definition: A standard property. Define the 'ERA' of the SEC48 address and length of the SEC 6 configuration registers.[all …]
2 SEC 4 Device Tree Binding7 -SEC 4 Node15 NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator23 SEC 4 h/w can process requests from 2 types of sources.25 2. Job Rings (HW interface between cores & SEC 4 registers).29 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts32 SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus42 SEC 4 Node46 Node defines the base address of the SEC 4 block.48 configuration registers for the SEC 4 block. It[all …]
1 * Hisilicon hip07 Security Accelerator (SEC)16 Interrupt 0 is for the SEC unit error queue.22 - iommus: The SEC units are behind smmu-v3 iommus.
15 SEC is the SOC's security engine, which serves as NXP's latest cryptographic20 integrity checking, and a hardware random number generator. SEC performs32 queues, queue portals to store and to enqueue/dequeue data to the hardware SEC.52 SEC provides platform assurance by working with SecMon, which is a companion53 logic block that tracks the security state of the SOC. SEC is programmed by56 associated data. SEC incorporates two DMA engines to fetch the descriptors,58 engine provides a scatter/gather capability so that SEC can read and write59 data scattered in memory. SEC may be configured by means of software for61 of SEC is little-endian mode.73 | MC SEC object |.......| Mempool |[all …]
8 The caam_jr PMD provides poll mode crypto driver support for NXP SEC 4.x+ (CAAM)16 SEC is the SOC's security engine, which serves as NXP's latest cryptographic21 integrity checking, and a hardware random number generator. SEC performs25 SEC HW accelerator above 4.x+ version are also known as CAAM.34 SEC provides platform assurance by working with SecMon, which is a companion35 logic block that tracks the security state of the SOC. SEC is programmed by38 associated data. SEC incorporates two DMA engines to fetch the descriptors,40 engine provides a scatter/gather capability so that SEC can read and write41 data scattered in memory. SEC may be configured by means of software for43 of SEC is little-endian mode.
15 SEC is the SOC's security engine, which serves as NXP's latest cryptographic20 integrity checking, and a hardware random number generator. SEC performs31 queues, queue portals to store and to enqueue/dequeue data to the hardware SEC.36 SEC provides platform assurance by working with SecMon, which is a companion37 logic block that tracks the security state of the SOC. SEC is programmed by40 associated data. SEC incorporates two DMA engines to fetch the descriptors,42 engine provides a scatter/gather capability so that SEC can read and write43 data scattered in memory. SEC may be configured by means of software for45 of SEC is little-endian mode.95 or to disable all 4 SEC devices
34 #ifndef SEC35 #define SEC 1 macro71 #define NSEC2SEC(n) ((n) / (NANOSEC / SEC))75 #define SEC2NSEC(m) ((hrtime_t)(m) * (NANOSEC / SEC))
40 #define SEC 1 macro51 #define NSEC2SEC(n) ((n) / (NANOSEC / SEC))52 #define SEC2NSEC(m) ((hrtime_t)(m) * (NANOSEC / SEC))
38 #define SEC 1 macro50 #define NSEC2SEC(n) ((n) / (NANOSEC / SEC))51 #define SEC2NSEC(m) ((hrtime_t)(m) * (NANOSEC / SEC))
861 #define VFS_CHECKEXP(MP, NAM, EXFLG, CRED, NUMSEC, SEC) ({ \ argument865 SEC); \
96 0x6 0x4>; /* ECC SEC Error */
110 0x6 0x4>; /* ECC SEC Error */
97 0x6 0x4 /* ECC SEC Error */ >;
106 0x6 0x4>; /* ECC SEC Error */
58 - SEC - Cryptographic accelerator
181 * **Added NXP DPAA SEC crypto PMD.**
291 * **Added NXP DPAA2 SEC crypto PMD.**