1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2019 Marvell International Ltd. 3 */ 4 5 #ifndef _OTX2_EP_RAWDEV_H_ 6 #define _OTX2_EP_RAWDEV_H_ 7 8 #include <rte_byteorder.h> 9 #include <rte_spinlock.h> 10 11 /* IQ instruction req types */ 12 #define SDP_REQTYPE_NONE (0) 13 #define SDP_REQTYPE_NORESP (1) 14 #define SDP_REQTYPE_NORESP_GATHER (2) 15 16 /* Input Request Header format */ 17 struct sdp_instr_irh { 18 /* Request ID */ 19 uint64_t rid:16; 20 21 /* PCIe port to use for response */ 22 uint64_t pcie_port:3; 23 24 /* Scatter indicator 1=scatter */ 25 uint64_t scatter:1; 26 27 /* Size of Expected result OR no. of entries in scatter list */ 28 uint64_t rlenssz:14; 29 30 /* Desired destination port for result */ 31 uint64_t dport:6; 32 33 /* Opcode Specific parameters */ 34 uint64_t param:8; 35 36 /* Opcode for the return packet */ 37 uint64_t opcode:16; 38 }; 39 40 /* SDP 32B instruction format */ 41 struct sdp_instr_32B { 42 /* Pointer where the input data is available. */ 43 uint64_t dptr; 44 45 /* SDP Instruction Header. */ 46 uint64_t ih; 47 48 /** Pointer where the response for a RAW mode packet 49 * will be written by OCTEON TX2. 50 */ 51 uint64_t rptr; 52 53 /* Input Request Header. Additional info about the input. */ 54 uint64_t irh; 55 }; 56 #define SDP_32B_INSTR_SIZE (sizeof(sdp_instr_32B)) 57 58 /* SDP 64B instruction format */ 59 struct sdp_instr_64B { 60 /* Pointer where the input data is available. */ 61 uint64_t dptr; 62 63 /* SDP Instruction Header. */ 64 uint64_t ih; 65 66 /** Pointer where the response for a RAW mode packet 67 * will be written by OCTEON TX2. 68 */ 69 uint64_t rptr; 70 71 /* Input Request Header. */ 72 uint64_t irh; 73 74 /* Additional headers available in a 64-byte instruction. */ 75 uint64_t exhdr[4]; 76 }; 77 #define SDP_64B_INSTR_SIZE (sizeof(sdp_instr_64B)) 78 79 struct sdp_soft_instr { 80 /** Input data pointer. It is either pointing directly to input data 81 * or to a gather list. 82 */ 83 void *dptr; 84 85 /** Response from OCTEON TX2 comes at this address. It is either 86 * directlty pointing to output data buffer or to a scatter list. 87 */ 88 void *rptr; 89 90 /* The instruction header. All input commands have this field. */ 91 struct sdp_instr_ih ih; 92 93 /* Input request header. */ 94 struct sdp_instr_irh irh; 95 96 /** The PCI instruction to be sent to OCTEON TX2. This is stored in the 97 * instr to retrieve the physical address of buffers when instr is 98 * freed. 99 */ 100 struct sdp_instr_64B command; 101 102 /** If a gather list was allocated, this ptr points to the buffer used 103 * for the gather list. The gather list has to be 8B aligned, so this 104 * value may be different from dptr. 105 */ 106 void *gather_ptr; 107 108 /* Total data bytes transferred in the gather mode request. */ 109 uint64_t gather_bytes; 110 111 /** If a scatter list was allocated, this ptr points to the buffer used 112 * for the scatter list. The scatter list has to be 8B aligned, so 113 * this value may be different from rptr. 114 */ 115 void *scatter_ptr; 116 117 /* Total data bytes to be received in the scatter mode request. */ 118 uint64_t scatter_bytes; 119 120 /* IQ number to which this instruction has to be submitted. */ 121 uint32_t q_no; 122 123 /* IQ instruction request type. */ 124 uint32_t reqtype; 125 }; 126 #define SDP_SOFT_INSTR_SIZE (sizeof(sdp_soft_instr)) 127 128 /* SDP IQ request list */ 129 struct sdp_instr_list { 130 void *buf; 131 uint32_t reqtype; 132 }; 133 #define SDP_IQREQ_LIST_SIZE (sizeof(struct sdp_instr_list)) 134 135 /* Input Queue statistics. Each input queue has four stats fields. */ 136 struct sdp_iq_stats { 137 uint64_t instr_posted; /* Instructions posted to this queue. */ 138 uint64_t instr_processed; /* Instructions processed in this queue. */ 139 uint64_t instr_dropped; /* Instructions that could not be processed */ 140 }; 141 142 /* Structure to define the configuration attributes for each Input queue. */ 143 struct sdp_iq_config { 144 /* Max number of IQs available */ 145 uint16_t max_iqs; 146 147 /* Command size - 32 or 64 bytes */ 148 uint16_t instr_type; 149 150 /* Pending list size, usually set to the sum of the size of all IQs */ 151 uint32_t pending_list_size; 152 }; 153 154 /** The instruction (input) queue. 155 * The input queue is used to post raw (instruction) mode data or packet data 156 * to OCTEON TX2 device from the host. Each IQ of a SDP EP VF device has one 157 * such structure to represent it. 158 */ 159 struct sdp_instr_queue { 160 /* A spinlock to protect access to the input ring. */ 161 rte_spinlock_t lock; 162 rte_spinlock_t post_lock; 163 164 struct sdp_device *sdp_dev; 165 rte_atomic64_t iq_flush_running; 166 167 uint32_t q_no; 168 uint32_t pkt_in_done; 169 170 /* Flag for 64 byte commands. */ 171 uint32_t iqcmd_64B:1; 172 uint32_t rsvd:17; 173 uint32_t status:8; 174 175 /* Number of descriptors in this ring. */ 176 uint32_t nb_desc; 177 178 /* Input ring index, where the driver should write the next packet */ 179 uint32_t host_write_index; 180 181 /* Input ring index, where the OCTEON TX2 should read the next packet */ 182 uint32_t otx_read_index; 183 184 /** This index aids in finding the window in the queue where OCTEON TX2 185 * has read the commands. 186 */ 187 uint32_t flush_index; 188 189 /* This keeps track of the instructions pending in this queue. */ 190 rte_atomic64_t instr_pending; 191 192 uint32_t reset_instr_cnt; 193 194 /* Pointer to the Virtual Base addr of the input ring. */ 195 uint8_t *base_addr; 196 197 /* This IQ request list */ 198 struct sdp_instr_list *req_list; 199 200 /* SDP doorbell register for the ring. */ 201 void *doorbell_reg; 202 203 /* SDP instruction count register for this ring. */ 204 void *inst_cnt_reg; 205 206 /* Number of instructions pending to be posted to OCTEON TX2. */ 207 uint32_t fill_cnt; 208 209 /* Statistics for this input queue. */ 210 struct sdp_iq_stats stats; 211 212 /* DMA mapped base address of the input descriptor ring. */ 213 uint64_t base_addr_dma; 214 215 /* Memory zone */ 216 const struct rte_memzone *iq_mz; 217 }; 218 219 /* DROQ packet format for application i/f. */ 220 struct sdp_droq_pkt { 221 /* DROQ packet data buffer pointer. */ 222 uint8_t *data; 223 224 /* DROQ packet data length */ 225 uint32_t len; 226 227 uint32_t misc; 228 }; 229 230 /** Descriptor format. 231 * The descriptor ring is made of descriptors which have 2 64-bit values: 232 * -# Physical (bus) address of the data buffer. 233 * -# Physical (bus) address of a sdp_droq_info structure. 234 * The device DMA's incoming packets and its information at the address 235 * given by these descriptor fields. 236 */ 237 struct sdp_droq_desc { 238 /* The buffer pointer */ 239 uint64_t buffer_ptr; 240 241 /* The Info pointer */ 242 uint64_t info_ptr; 243 }; 244 #define SDP_DROQ_DESC_SIZE (sizeof(struct sdp_droq_desc)) 245 246 /* Receive Header */ 247 union sdp_rh { 248 uint64_t rh64; 249 }; 250 #define SDP_RH_SIZE (sizeof(union sdp_rh)) 251 252 /** Information about packet DMA'ed by OCTEON TX2. 253 * The format of the information available at Info Pointer after OCTEON TX2 254 * has posted a packet. Not all descriptors have valid information. Only 255 * the Info field of the first descriptor for a packet has information 256 * about the packet. 257 */ 258 struct sdp_droq_info { 259 /* The Output Receive Header. */ 260 union sdp_rh rh; 261 262 /* The Length of the packet. */ 263 uint64_t length; 264 }; 265 #define SDP_DROQ_INFO_SIZE (sizeof(struct sdp_droq_info)) 266 267 /** Pointer to data buffer. 268 * Driver keeps a pointer to the data buffer that it made available to 269 * the OCTEON TX2 device. Since the descriptor ring keeps physical (bus) 270 * addresses, this field is required for the driver to keep track of 271 * the virtual address pointers. 272 */ 273 struct sdp_recv_buffer { 274 /* Packet buffer, including meta data. */ 275 void *buffer; 276 277 /* Data in the packet buffer. */ 278 /* uint8_t *data; */ 279 }; 280 #define SDP_DROQ_RECVBUF_SIZE (sizeof(struct sdp_recv_buffer)) 281 282 /* DROQ statistics. Each output queue has four stats fields. */ 283 struct sdp_droq_stats { 284 /* Number of packets received in this queue. */ 285 uint64_t pkts_received; 286 287 /* Bytes received by this queue. */ 288 uint64_t bytes_received; 289 290 /* Num of failures of rte_pktmbuf_alloc() */ 291 uint64_t rx_alloc_failure; 292 }; 293 294 /* Structure to define the configuration attributes for each Output queue. */ 295 struct sdp_oq_config { 296 /* Max number of OQs available */ 297 uint16_t max_oqs; 298 299 /* If set, the Output queue uses info-pointer mode. (Default: 1 ) */ 300 uint16_t info_ptr; 301 302 /** The number of buffers that were consumed during packet processing by 303 * the driver on this Output queue before the driver attempts to 304 * replenish the descriptor ring with new buffers. 305 */ 306 uint32_t refill_threshold; 307 }; 308 309 /* The Descriptor Ring Output Queue(DROQ) structure. */ 310 struct sdp_droq { 311 /* A spinlock to protect access to this ring. */ 312 rte_spinlock_t lock; 313 314 struct sdp_device *sdp_dev; 315 /* The 8B aligned descriptor ring starts at this address. */ 316 struct sdp_droq_desc *desc_ring; 317 318 uint32_t q_no; 319 uint32_t last_pkt_count; 320 321 /* Driver should read the next packet at this index */ 322 uint32_t read_idx; 323 324 /* OCTEON TX2 will write the next packet at this index */ 325 uint32_t write_idx; 326 327 /* At this index, the driver will refill the descriptor's buffer */ 328 uint32_t refill_idx; 329 330 /* Packets pending to be processed */ 331 rte_atomic64_t pkts_pending; 332 333 /* Number of descriptors in this ring. */ 334 uint32_t nb_desc; 335 336 /* The number of descriptors pending to refill. */ 337 uint32_t refill_count; 338 339 uint32_t refill_threshold; 340 341 /* The 8B aligned info ptrs begin from this address. */ 342 struct sdp_droq_info *info_list; 343 344 /* receive buffer list contains virtual addresses of the buffers. */ 345 struct sdp_recv_buffer *recv_buf_list; 346 347 /* The size of each buffer pointed by the buffer pointer. */ 348 uint32_t buffer_size; 349 350 /** Pointer to the mapped packet credit register. 351 * Host writes number of info/buffer ptrs available to this register 352 */ 353 void *pkts_credit_reg; 354 355 /** Pointer to the mapped packet sent register. OCTEON TX2 writes the 356 * number of packets DMA'ed to host memory in this register. 357 */ 358 void *pkts_sent_reg; 359 360 /* Statistics for this DROQ. */ 361 struct sdp_droq_stats stats; 362 363 /* DMA mapped address of the DROQ descriptor ring. */ 364 size_t desc_ring_dma; 365 366 /* Info_ptr list is allocated at this virtual address. */ 367 size_t info_base_addr; 368 369 /* DMA mapped address of the info list */ 370 size_t info_list_dma; 371 372 /* Allocated size of info list. */ 373 uint32_t info_alloc_size; 374 375 /* Memory zone **/ 376 const struct rte_memzone *desc_ring_mz; 377 const struct rte_memzone *info_mz; 378 }; 379 #define SDP_DROQ_SIZE (sizeof(struct sdp_droq)) 380 381 /* IQ/OQ mask */ 382 struct sdp_io_enable { 383 uint64_t iq; 384 uint64_t oq; 385 uint64_t iq64B; 386 }; 387 388 /* Structure to define the configuration. */ 389 struct sdp_config { 390 /* Input Queue attributes. */ 391 struct sdp_iq_config iq; 392 393 /* Output Queue attributes. */ 394 struct sdp_oq_config oq; 395 396 /* Num of desc for IQ rings */ 397 uint32_t num_iqdef_descs; 398 399 /* Num of desc for OQ rings */ 400 uint32_t num_oqdef_descs; 401 402 /* OQ buffer size */ 403 uint32_t oqdef_buf_size; 404 }; 405 406 /* Required functions for each VF device */ 407 struct sdp_fn_list { 408 void (*setup_iq_regs)(struct sdp_device *sdpvf, uint32_t q_no); 409 void (*setup_oq_regs)(struct sdp_device *sdpvf, uint32_t q_no); 410 411 int (*setup_device_regs)(struct sdp_device *sdpvf); 412 uint32_t (*update_iq_read_idx)(struct sdp_instr_queue *iq); 413 414 void (*enable_io_queues)(struct sdp_device *sdpvf); 415 void (*disable_io_queues)(struct sdp_device *sdpvf); 416 417 void (*enable_iq)(struct sdp_device *sdpvf, uint32_t q_no); 418 void (*disable_iq)(struct sdp_device *sdpvf, uint32_t q_no); 419 420 void (*enable_oq)(struct sdp_device *sdpvf, uint32_t q_no); 421 void (*disable_oq)(struct sdp_device *sdpvf, uint32_t q_no); 422 }; 423 424 /* SRIOV information */ 425 struct sdp_sriov_info { 426 /* Number of rings assigned to VF */ 427 uint32_t rings_per_vf; 428 429 /* Number of VF devices enabled */ 430 uint32_t num_vfs; 431 }; 432 433 434 /* Information to be passed from application */ 435 struct sdp_rawdev_info { 436 struct rte_mempool *enqdeq_mpool; 437 const struct sdp_config *app_conf; 438 }; 439 440 /* SDP EP VF device */ 441 struct sdp_device { 442 /* PCI device pointer */ 443 struct rte_pci_device *pci_dev; 444 uint16_t chip_id; 445 uint16_t pf_num; 446 uint16_t vf_num; 447 448 /* This device's PCIe port used for traffic. */ 449 uint16_t pcie_port; 450 uint32_t pkind; 451 452 /* The state of this device */ 453 rte_atomic64_t status; 454 455 /* Memory mapped h/w address */ 456 uint8_t *hw_addr; 457 458 struct sdp_fn_list fn_list; 459 460 /* Num IQs */ 461 uint32_t num_iqs; 462 463 /* The input instruction queues */ 464 struct sdp_instr_queue *instr_queue[SDP_VF_MAX_IOQS_PER_RAWDEV]; 465 466 /* Num OQs */ 467 uint32_t num_oqs; 468 469 /* The DROQ output queues */ 470 struct sdp_droq *droq[SDP_VF_MAX_IOQS_PER_RAWDEV]; 471 472 /* IOQ data buffer pool */ 473 struct rte_mempool *enqdeq_mpool; 474 475 /* IOQ mask */ 476 struct sdp_io_enable io_qmask; 477 478 /* SR-IOV info */ 479 struct sdp_sriov_info sriov_info; 480 481 /* Device configuration */ 482 const struct sdp_config *conf; 483 }; 484 485 const struct sdp_config *sdp_get_defconf(struct sdp_device *sdp_dev); 486 int sdp_setup_iqs(struct sdp_device *sdpvf, uint32_t iq_no); 487 int sdp_delete_iqs(struct sdp_device *sdpvf, uint32_t iq_no); 488 489 int sdp_setup_oqs(struct sdp_device *sdpvf, uint32_t oq_no); 490 int sdp_delete_oqs(struct sdp_device *sdpvf, uint32_t oq_no); 491 492 int sdp_rawdev_enqueue(struct rte_rawdev *dev, struct rte_rawdev_buf **buffers, 493 unsigned int count, rte_rawdev_obj_t context); 494 int sdp_rawdev_dequeue(struct rte_rawdev *dev, struct rte_rawdev_buf **buffers, 495 unsigned int count, rte_rawdev_obj_t context); 496 497 int sdp_rawdev_selftest(uint16_t dev_id); 498 499 #endif /* _OTX2_EP_RAWDEV_H_ */ 500