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Searched refs:SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE (Results 1 – 4 of 4) sorted by relevance

/f-stack/freebsd/arm/nvidia/tegra124/
H A Dtegra124_car.h223 #define SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE (1 << 7) macro
H A Dtegra124_clk_pll.c656 reg &= ~SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE; in plle_enable()
/f-stack/freebsd/arm64/nvidia/tegra210/
H A Dtegra210_car.h308 #define SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE (1 << 7) macro
H A Dtegra210_clk_pll.c855 reg &= ~SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE; in plle_enable()