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Searched refs:RM1 (Results 1 – 9 of 9) sorted by relevance

/f-stack/freebsd/arm/nvidia/
H A Das3722_regulators.c408 rv = RM1(sc->base_sc, sc->def->volt_reg, in as3722_write_sel()
434 rv = RM1(sc->base_sc, sc->def->ext_enable_reg, in as3722_reg_extreg_setup()
444 rv = RM1(sc->base_sc, sc->def->enable_reg, in as3722_reg_enable()
454 rv = RM1(sc->base_sc, sc->def->enable_reg, in as3722_reg_disable()
476 rv = RM1(sc->base_sc, sc->def->volt_reg, in as3722_regnode_init()
H A Das3722_rtc.c105 rv = RM1(sc, AS3722_RTC_CONTROL, in as3722_rtc_attach()
H A Das3722_gpio.c472 rv = RM1(sc, AS3722_GPIO_SIGNAL_OUT, (1 << pin), (tmp << pin)); in as3722_gpio_pin_set()
524 rv = RM1(sc, AS3722_GPIO_SIGNAL_OUT, (1 << pin), tmp); in as3722_gpio_pin_toggle()
H A Das3722.h287 #define RM1(sc, reg, clr, set) as3722_modify(sc, reg, clr, set) macro
H A Das3722.c229 rv = RM1(sc, AS3722_IO_VOLTAGE, in as3722_init()
/f-stack/freebsd/arm64/nvidia/tegra210/
H A Dmax77620_regulators.c387 rv = RM1(sc->base_sc, sc->def->volt_reg, in max77620_set_sel()
416 rv = RM1(sc->base_sc, sc->def->fps_reg, MAX77620_FPS_SRC_MASK, in max77620_set_fps_src()
451 rv = RM1(sc->base_sc, sc->def->fps_reg, mask, val); in max77620_set_fps_slots()
476 rv = RM1(sc->base_sc, sc->def->pwr_mode_reg, sc->def->pwr_mode_shift, in max77620_set_pwr_mode()
541 rv = RM1(sc->base_sc, sc->def->cfg_reg, mask, val); in max77620_set_pwr_ramp_delay()
H A Dmax77620.c319 rv = RM1(sc, MAX77620_REG_FPS_CFG0 + i, mask, val); in max77620_init()
327 rv = RM1(sc, MAX77620_REG_INTENLBT, 0x81, 0x81); in max77620_init()
328 rv = RM1(sc, MAX77620_REG_IRQTOPM, 0x81, 0x81); in max77620_init()
H A Dmax77620.h228 #define RM1(sc, reg, clr, set) max77620_modify(sc, reg, clr, set) macro
H A Dmax77620_gpio.c603 rv = RM1(sc, sc->gpio_pins[pin]->reg, MAX77620_REG_GPIO_OUTPUT_VAL(~0), in max77620_gpio_pin_set()
652 rv = RM1(sc, sc->gpio_pins[pin]->reg, MAX77620_REG_GPIO_OUTPUT_VAL(~0), in max77620_gpio_pin_toggle()