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Searched refs:REG_RD (Results 1 – 12 of 12) sorted by relevance

/f-stack/dpdk/drivers/net/bnx2x/
H A Dbnx2x.c3731 REG_RD(sc, in bnx2x_mc_assert()
3734 REG_RD(sc, in bnx2x_mc_assert()
3738 REG_RD(sc, in bnx2x_mc_assert()
3742 REG_RD(sc, in bnx2x_mc_assert()
3767 REG_RD(sc, in bnx2x_mc_assert()
3770 REG_RD(sc, in bnx2x_mc_assert()
3774 REG_RD(sc, in bnx2x_mc_assert()
3778 REG_RD(sc, in bnx2x_mc_assert()
3803 REG_RD(sc, in bnx2x_mc_assert()
3806 REG_RD(sc, in bnx2x_mc_assert()
[all …]
H A Delink.c938 uint32_t val = REG_RD(sc, reg); in elink_bits_en()
948 uint32_t val = REG_RD(sc, reg); in elink_bits_dis()
971 REG_RD(sc, params->lfa_base + in elink_check_lfa()
1056 REG_RD(sc, params->lfa_base + in elink_check_lfa()
6998 latch_status = REG_RD(sc, in elink_rearm_latch_signal()
7714 val = REG_RD(sc, addr) + 1; in elink_chng_link_count()
13054 rx = REG_RD(sc, shmem_base + in elink_populate_preemphasis()
13058 tx = REG_RD(sc, shmem_base + in elink_populate_preemphasis()
13121 phy_addr = REG_RD(sc, in elink_populate_int_phy()
13213 phy_addr = REG_RD(sc, in elink_populate_int_phy()
[all …]
H A Decore_init.h210 uint32_t curr_cos = REG_RD(sc, QM_REG_QVOQIDX_0 + q_num * 4); in ecore_map_q_cos()
237 reg_bit_map = REG_RD(sc, reg_addr); in ecore_map_q_cos()
242 reg_bit_map = REG_RD(sc, reg_addr); in ecore_map_q_cos()
249 reg_bit_map = REG_RD(sc, reg_addr); in ecore_map_q_cos()
715 reg_val = REG_RD(sc, mcp_attn_ctl_regs[i].addr); in ecore_set_mcp_parity()
780 reg_val = REG_RD(sc, ecore_blocks_parity_data[i]. in ecore_clear_blocks_parity()
790 reg_val = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_MCP); in ecore_clear_blocks_parity()
H A Decore_init_ops.h214 REG_RD(sc, addr); in ecore_init_block()
470 val = REG_RD(sc, write_arb_addr[i].l); in ecore_init_pxp_arb()
474 val = REG_RD(sc, write_arb_addr[i].add); in ecore_init_pxp_arb()
478 val = REG_RD(sc, write_arb_addr[i].ubound); in ecore_init_pxp_arb()
539 val = REG_RD(sc, PCIE_REG_PCIER_TL_HDR_FC_ST); in ecore_init_pxp_arb()
H A Dbnx2x.h1530 #define REG_RD(sc, offset) REG_RD32(sc, offset) macro
1592 #define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field))
1599 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \
1601 #define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field))
1606 #define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field))
1863 val = REG_RD(sc, reg); in reg_poll()
1927 uint32_t result = REG_RD(sc, hc_addr); in bnx2x_hc_ack_int()
1937 uint32_t result = REG_RD(sc, igu_addr); in bnx2x_igu_ack_int()
H A Dbnx2x_stats.c833 estats->eee_tx_lpi += REG_RD(sc, lpi_reg); in bnx2x_hw_stats_update()
1490 REG_RD(sc, NIG_REG_STAT0_BRB_DISCARD + port*0x38); in bnx2x_stats_init()
1492 REG_RD(sc, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38); in bnx2x_stats_init()
H A Dbnx2x_ethdev.c121 link_status = REG_RD(sc, sc->link_params.shmem_base + in bnx2x_interrupt_action()
/f-stack/dpdk/drivers/net/qede/base/
H A Decore_hw.c249 is_empty = REG_RD(p_hwfn, bar_addr) == 0; in ecore_is_reg_fifo_empty()
292 val = REG_RD(p_hwfn, bar_addr); in ecore_rd()
H A Dbcm_osal.h127 #define REG_RD(_p_hwfn, _reg_offset) \ macro
H A Decore_dev.c2620 if (REG_RD(p_hwfn, addr)) { in ecore_final_cleanup()
2635 while (!REG_RD(p_hwfn, addr) && count--) in ecore_final_cleanup()
2638 if (REG_RD(p_hwfn, addr)) in ecore_final_cleanup()
4301 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, in get_function_id()
4304 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); in get_function_id()
5628 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { in ecore_hw_prepare_single()
H A Decore_vf.c540 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, reg); in ecore_vf_hw_prepare()
543 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, reg); in ecore_vf_hw_prepare()
H A Decore_int.c2580 intr_status_lo = REG_RD(p_hwfn, in ecore_int_igu_read_sisr_reg()
2583 intr_status_hi = REG_RD(p_hwfn, in ecore_int_igu_read_sisr_reg()