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Searched refs:RD4 (Results 1 – 25 of 65) sorted by relevance

123

/f-stack/freebsd/arm/nvidia/
H A Dtegra_efuse.c197 sku->sku_id = RD4(sc, TEGRA124_FUSE_SKU_INFO); in tegra124_init()
287 reg = RD4(sc, TEGRA210_FUSE_SPARE + 2 * 4); in tegra210_get_speedo_revision()
289 reg = RD4(sc, TEGRA210_FUSE_SPARE + 3 * 4); in tegra210_get_speedo_revision()
291 reg = RD4(sc, TEGRA210_FUSE_SPARE + 4 * 4); in tegra210_get_speedo_revision()
339 cpu_speedo[0] = RD4(sc, TEGRA210_FUSE_CPU_SPEEDO_0); in tegra210_init()
340 cpu_speedo[1] = RD4(sc, TEGRA210_FUSE_CPU_SPEEDO_1); in tegra210_init()
341 cpu_speedo[2] = RD4(sc, TEGRA210_FUSE_CPU_SPEEDO_2); in tegra210_init()
351 cpu_iddq = RD4(sc, TEGRA210_FUSE_CPU_IDDQ) * 4; in tegra210_init()
352 soc_iddq = RD4(sc, TEGRA210_FUSE_SOC_IDDQ) * 4; in tegra210_init()
353 gpu_iddq = RD4(sc, TEGRA210_FUSE_GPU_IDDQ) * 5; in tegra210_init()
[all …]
H A Dtegra_usbphy.c308 #define RD4(sc, offs) \ macro
356 val = RD4(sc, IF_USB_SUSP_CTRL); in usbphy_utmi_enable()
360 val = RD4(sc, UTMIP_TX_CFG0); in usbphy_utmi_enable()
364 val = RD4(sc, UTMIP_HSRX_CFG0); in usbphy_utmi_enable()
371 val = RD4(sc, UTMIP_HSRX_CFG1); in usbphy_utmi_enable()
381 val = RD4(sc, UTMIP_MISC_CFG0); in usbphy_utmi_enable()
434 val = RD4(sc, UTMIP_XCVR_CFG0); in usbphy_utmi_enable()
455 val = RD4(sc, UTMIP_XCVR_CFG1); in usbphy_utmi_enable()
463 val = RD4(sc, UTMIP_BIAS_CFG1); in usbphy_utmi_enable()
525 val = RD4(sc, UTMIP_XCVR_CFG0); in usbphy_utmi_disable()
[all …]
H A Dtegra_soctherm.c134 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro
548 RD4(sc, sensor->sensor_base + TSENSOR_CONFIG0), in soctherm_init_tsensor()
549 RD4(sc, sensor->sensor_base + TSENSOR_CONFIG1), in soctherm_init_tsensor()
550 RD4(sc, sensor->sensor_base + TSENSOR_CONFIG2), in soctherm_init_tsensor()
551 RD4(sc, sensor->sensor_base + TSENSOR_STATUS0), in soctherm_init_tsensor()
552 RD4(sc, sensor->sensor_base + TSENSOR_STATUS1), in soctherm_init_tsensor()
553 RD4(sc, sensor->sensor_base + TSENSOR_STATUS2) in soctherm_init_tsensor()
592 RD4(sc, sensor->sensor_base + TSENSOR_CONFIG0), in soctherm_read_temp()
593 RD4(sc, sensor->sensor_base + TSENSOR_CONFIG1), in soctherm_read_temp()
594 RD4(sc, sensor->sensor_base + TSENSOR_CONFIG2), in soctherm_read_temp()
[all …]
H A Dtegra_i2c.c244 reg = RD4(sc, I2C_FIFO_CONTROL); in tegra_i2c_flush_fifo()
250 reg = RD4(sc, I2C_FIFO_CONTROL); in tegra_i2c_flush_fifo()
292 if (RD4(sc, I2C_CONFIG_LOAD) == 0) in tegra_i2c_bus_clear()
298 reg = RD4(sc, I2C_BUS_CLEAR_CONFIG); in tegra_i2c_bus_clear()
303 if ((RD4(sc, I2C_BUS_CLEAR_CONFIG) & in tegra_i2c_bus_clear()
311 status = RD4(sc, I2C_BUS_CLEAR_STATUS); in tegra_i2c_bus_clear()
346 if (RD4(sc, I2C_CONFIG_LOAD) == 0) in tegra_i2c_hw_init()
367 reg = RD4(sc, I2C_FIFO_STATUS); in tegra_i2c_tx()
393 reg = RD4(sc, I2C_FIFO_STATUS); in tegra_i2c_rx()
397 reg = RD4(sc, I2C_RX_FIFO); in tegra_i2c_rx()
[all …]
/f-stack/freebsd/arm64/nvidia/tegra210/
H A Dtegra210_xusbpadctl.c1010 reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP); in usb3_port_init()
1054 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); in usb3_port_init()
1059 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); in usb3_port_init()
1064 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); in usb3_port_init()
1082 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in pcie_enable()
1094 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in pcie_disable()
1114 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in sata_enable()
1126 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in sata_disable()
1278 reg = RD4(sc, XUSB_PADCTL_USB2_PORT_CAP); in usb2_enable()
1382 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); in pad_common_enable()
[all …]
H A Dtegra210_pmc.c237 reg = RD4(sc, PMC_PWRGATE_TOGGLE); in tegra210_pmc_set_powergate()
277 reg = RD4(sc, PMC_PWRGATE_STATUS); in tegra_powergate_remove_clamping()
298 reg = RD4(sc, PMC_CLAMP_STATUS); in tegra_powergate_remove_clamping()
313 reg = RD4(sc, PMC_PWRGATE_STATUS); in tegra_powergate_is_powered()
508 orig = RD4(sc, PMC_SCRATCH0); in tegra210_pmc_check_secure()
510 if (RD4(sc, PMC_SCRATCH0) == 0) { in tegra210_pmc_check_secure()
515 if (RD4(sc, PMC_SCRATCH0) == 0) { in tegra210_pmc_check_secure()
580 reg = RD4(sc, PMC_CNTRL); in tegra210_pmc_attach()
585 reg = RD4(sc, PMC_CNTRL); in tegra210_pmc_attach()
593 reg = RD4(sc, PMC_CNTRL); in tegra210_pmc_attach()
[all …]
H A Dtegra210_clk_pll.c604 RD4(sc, sc->base_reg, &reg); in pll_enable()
617 RD4(sc, sc->base_reg, &reg); in pll_disable()
689 RD4(sc, sc->base_reg, &val); in get_divisors()
762 RD4(sc, sc->base_reg, &reg); in plle_enable()
767 RD4(sc, PLLE_AUX, &reg); in plle_enable()
821 RD4(sc, PLLE_AUX, &reg); in plle_enable()
1153 RD4(sc, PLLX_MISC_2, &reg); in pllx_set_freq()
1158 RD4(sc, PLLX_MISC_2, &reg); in pllx_set_freq()
1164 RD4(sc, PLLX_MISC_2, &reg); in pllx_set_freq()
1187 RD4(sc, PLLX_MISC_2, &reg); in pllx_set_freq()
[all …]
/f-stack/freebsd/arm/freescale/imx/
H A Dimx6_ccm.c68 RD4(struct ccm_softc *sc, bus_size_t off) in RD4() function
179 reg = RD4(sc, CCM_CGPR); in ccm_attach()
182 reg = RD4(sc, CCM_CLPCR); in ccm_attach()
226 reg = RD4(sc, CCM_CSCMR1); in imx_ccm_ssi_configure()
241 reg = RD4(sc, CCM_CS1CDR); in imx_ccm_ssi_configure()
255 reg = RD4(sc, CCM_CS2CDR); in imx_ccm_ssi_configure()
330 v = RD4(ccm_sc, CCM_ANALOG_PLL_ENET); in imx6_ccm_sata_enable()
450 reg = RD4(sc, CCM_CCGR3); in imx_ccm_ipu_enable()
458 reg = RD4(sc, CCM_CHSCCDR); in imx_ccm_ipu_enable()
483 reg = RD4(sc, CCM_CCGR2); in imx_ccm_hdmi_enable()
[all …]
H A Dimx6_snvs.c82 RD4(struct snvs_softc *sc, bus_size_t offset) in RD4() function
108 while ((RD4(sc, SNVS_LPCR) & LPCR_SRTC_ENV) != enbit) in snvs_rtc_enable()
121 if (!(RD4(sc, SNVS_LPCR) & LPCR_SRTC_ENV)) { in snvs_gettime()
133 counter1 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32); in snvs_gettime()
134 counter1 |= (uint64_t)RD4(sc, SNVS_LPSRTCLR) << (SBT_LSB); in snvs_gettime()
135 counter2 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32); in snvs_gettime()
136 counter2 |= (uint64_t)RD4(sc, SNVS_LPSRTCLR) << (SBT_LSB); in snvs_gettime()
H A Dimx6_src.c59 RD4(struct src_softc *sc, bus_size_t off) in RD4() function
81 reg = RD4(src_sc, SRC_SCR); in src_reset_ipu()
86 reg = RD4(src_sc, SRC_SCR); in src_reset_ipu()
/f-stack/freebsd/arm/broadcom/bcm2835/
H A Dbcm2835_sdhost.c257 val = RD4(sc, off & ~3); in RD2()
268 val = RD4(sc, off & ~3); in RD1()
278 val32 = RD4(sc, off & ~3); in WR2()
289 val32 = RD4(sc, off & ~3); in WR1()
304 RD4(sc, HC_COMMAND)); in bcm_sdhost_print_regs()
306 RD4(sc, HC_ARGUMENT)); in bcm_sdhost_print_regs()
322 RD4(sc, HC_POWER)); in bcm_sdhost_print_regs()
324 RD4(sc, HC_DEBUG)); in bcm_sdhost_print_regs()
359 dbg = RD4(sc, HC_DEBUG); in bcm_sdhost_reset()
566 cmd = RD4(sc, HC_COMMAND); in bcm_sdhost_intr()
[all …]
/f-stack/freebsd/arm/nvidia/tegra124/
H A Dtegra124_xusbpadctl.c371 reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP); in usb3_port_init()
392 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); in usb3_port_init()
397 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); in usb3_port_init()
402 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); in usb3_port_init()
443 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in pcie_powerup()
455 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in pcie_powerdown()
502 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in sata_powerup()
506 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in sata_powerup()
518 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in sata_powerdown()
647 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); in phy_powerup()
[all …]
H A Dtegra124_clk_pll.c418 RD4(sc, sc->base_reg, &reg); in pll_enable()
431 RD4(sc, sc->base_reg, &reg); in pll_disable()
496 RD4(sc, sc->base_reg, &val); in get_divisors()
570 RD4(sc, sc->base_reg, &reg); in plle_enable()
574 RD4(sc, PLLE_AUX, &reg); in plle_enable()
580 RD4(sc, sc->misc_reg, &reg); in plle_enable()
590 RD4(sc, PLLE_SS_CNTL, &reg); in plle_enable()
594 RD4(sc, sc->base_reg, &reg); in plle_enable()
606 RD4(sc, PLLE_SS_CNTL, &reg); in plle_enable()
622 RD4(sc, sc->misc_reg, &reg); in plle_enable()
[all …]
H A Dtegra124_pmc.c200 reg = RD4(sc, PMC_PWRGATE_TOGGLE); in tegra124_pmc_set_powergate()
213 reg = RD4(sc, PMC_PWRGATE_TOGGLE); in tegra124_pmc_set_powergate()
240 reg = RD4(sc, PMC_PWRGATE_STATUS); in tegra_powergate_remove_clamping()
253 reg = RD4(sc, PMC_REMOVE_CLAMPING_CMD); in tegra_powergate_remove_clamping()
261 reg = RD4(sc, PMC_CLAMP_STATUS); in tegra_powergate_remove_clamping()
276 reg = RD4(sc, PMC_PWRGATE_STATUS); in tegra_powergate_is_powered()
514 reg = RD4(sc, PMC_CNTRL); in tegra124_pmc_attach()
519 reg = RD4(sc, PMC_CNTRL); in tegra124_pmc_attach()
527 reg = RD4(sc, PMC_CNTRL); in tegra124_pmc_attach()
535 reg = RD4(sc, PMC_IO_DPD_STATUS); in tegra124_pmc_attach()
[all …]
H A Dtegra124_clk_super.c162 RD4(sc, sc->base_reg, &reg); in super_mux_init()
200 RD4(sc, sc->base_reg, &reg); in super_mux_set_mux()
214 RD4(sc, sc->base_reg, &dummy); in super_mux_set_mux()
218 RD4(sc, sc->base_reg, &dummy); in super_mux_set_mux()
225 RD4(sc, sc->base_reg, &dummy); in super_mux_set_mux()
/f-stack/freebsd/arm/xilinx/
H A Dzy7_gpio.c99 #define RD4(sc, off) bus_read_4((sc)->mem_res, (off)) macro
179 if ((RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & (1 << (pin & 31))) != 0) { in zy7_gpio_pin_getflags()
181 if ((RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & (1 << (pin & 31))) == 0) in zy7_gpio_pin_getflags()
208 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) | (1 << (pin & 31))); in zy7_gpio_pin_setflags()
212 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & in zy7_gpio_pin_setflags()
216 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) | in zy7_gpio_pin_setflags()
221 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & ~(1 << (pin & 31))); in zy7_gpio_pin_setflags()
223 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & ~(1 << (pin & 31))); in zy7_gpio_pin_setflags()
262 *value = (RD4(sc, ZY7_GPIO_DATA_RO(pin >> 5)) >> (pin & 31)) & 1; in zy7_gpio_pin_get()
279 RD4(sc, ZY7_GPIO_DATA(pin >> 5)) ^ (1 << (pin & 31))); in zy7_gpio_pin_toggle()
H A Dzy7_slcr.c142 RD4(sc, ZY7_SLCR_REBOOT_STAT) & 0xf0ffffff); in zy7_slcr_cpu_reset()
276 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); in zy7_pl_fclk_set_source()
302 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); in zy7_pl_fclk_get_source()
366 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); in zy7_pl_fclk_set_freq()
415 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); in zy7_pl_fclk_get_freq()
495 reg = RD4(sc, ZY7_SLCR_FPGA_THR_CNT(unit)); in zy7_pl_fclk_enabled()
512 reg = RD4(sc, ZY7_SLCR_LVL_SHFTR_EN); in zy7_pl_level_shifters_enabled()
601 bootmode = RD4(sc, ZY7_SLCR_BOOT_MODE); in zy7_slcr_attach()
606 pss_idcode = RD4(sc, ZY7_SLCR_PSS_IDCODE); in zy7_slcr_attach()
631 arm_pll_ctrl = RD4(sc, ZY7_SLCR_ARM_PLL_CTRL); in zy7_slcr_attach()
[all …]
H A Duart_dev_cdnc.c57 #define RD4(bas, reg) \ macro
336 while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) & in cdnc_uart_putc()
342 while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) & in cdnc_uart_putc()
354 return ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & in cdnc_uart_rxready()
368 while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & in cdnc_uart_getc()
375 c = RD4(bas, CDNC_UART_FIFO); in cdnc_uart_getc()
518 status = RD4(bas, CDNC_UART_ISTAT_REG); in cdnc_uart_bus_receive()
528 while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & in cdnc_uart_bus_receive()
530 c = RD4(bas, CDNC_UART_FIFO) & 0xff; in cdnc_uart_bus_receive()
566 istatus = RD4(bas, CDNC_UART_ISTAT_REG); in cdnc_uart_bus_ipend()
[all …]
H A Dzy7_devcfg.c101 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) macro
420 WR4(sc, ZY7_DEVCFG_MCTRL, RD4(sc, ZY7_DEVCFG_MCTRL) & in zy7_devcfg_init_hw()
433 devcfg_ctl = RD4(sc, ZY7_DEVCFG_CTRL); in zy7_devcfg_reset_pl()
447 if ((RD4(sc, ZY7_DEVCFG_STATUS) & in zy7_devcfg_reset_pl()
465 while ((RD4(sc, ZY7_DEVCFG_STATUS) & in zy7_devcfg_reset_pl()
574 if ((RD4(sc, ZY7_DEVCFG_INT_STATUS) & in zy7_devcfg_write()
620 if ((RD4(sc, ZY7_DEVCFG_INT_STATUS) & in zy7_devcfg_write()
654 istatus = RD4(sc, ZY7_DEVCFG_INT_STATUS); in zy7_devcfg_intr()
655 imask = ~RD4(sc, ZY7_DEVCFG_INT_MASK); in zy7_devcfg_intr()
689 pl_done = ((RD4(sc, ZY7_DEVCFG_INT_STATUS) & in zy7_devcfg_sysctl_pl_done()
[all …]
/f-stack/freebsd/arm/mv/
H A Dmv_thermal.c126 #define RD4(sc, reg) \ macro
147 reg = RD4(sc, STATUS); in mv_thermal_wait_sensor()
168 reg = RD4(sc, CONTROL0); in mv_thermal_select_sensor()
190 reg = RD4(sc, CONTROL0); in mv_thermal_select_sensor()
207 reg = RD4(sc, STATUS) & STATUS_TEMP_MASK; in mv_thermal_read_sensor()
226 reg = RD4(sc, CONTROL0); in ap806_init()
246 reg = RD4(sc, CONTROL1); in cp110_init()
252 reg = RD4(sc, CONTROL0); in cp110_init()
/f-stack/freebsd/arm64/rockchip/
H A Drk_tsadc.c407 val = RD4(sc, TSADC_INT_EN); in tsadc_init_tsensor()
421 val = RD4(sc, TSADC_AUTO_CON); in tsadc_init_tsensor()
428 val = RD4(sc, TSADC_INT_EN); in tsadc_init_tsensor()
484 val = RD4(sc, TSADC_DATA(sensor->channel)); in tsadc_read_temp()
491 RD4(sc, TSADC_USER_CON), in tsadc_read_temp()
492 RD4(sc, TSADC_AUTO_CON)); in tsadc_read_temp()
494 RD4(sc, TSADC_DATA(sensor->channel)), in tsadc_read_temp()
495 RD4(sc, TSADC_COMP_INT(sensor->channel)), in tsadc_read_temp()
496 RD4(sc, TSADC_COMP_SHUT(sensor->channel))); in tsadc_read_temp()
583 val = RD4(sc, TSADC_INT_PD); in tsadc_intr()
[all …]
H A Drk_pcie_phy.c100 #define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg)) macro
113 RD4(sc, GRF_SOC_CON8); in cfg_write()
117 RD4(sc, GRF_SOC_CON8); in cfg_write()
120 RD4(sc, GRF_SOC_CON8); in cfg_write()
130 RD4(sc, GRF_SOC_CON8); in cfg_read()
132 val = RD4(sc, GRF_SOC_STATUS1); in cfg_read()
/f-stack/freebsd/arm64/broadcom/genet/
H A Dif_genet.c475 val = RD4(sc, GENET_RBUF_CTRL); in gen_reset()
488 val = RD4(sc, GENET_UMAC_CMD); in gen_enable()
531 val = RD4(sc, GENET_TX_DMA_CTRL); in gen_dma_disable()
536 val = RD4(sc, GENET_RX_DMA_CTRL); in gen_dma_disable()
693 val = RD4(sc, GENET_TX_DMA_CTRL); in gen_init_txring()
743 val = RD4(sc, GENET_RX_DMA_CTRL); in gen_init_rxring()
880 cmd = RD4(sc, GENET_UMAC_CMD); in gen_setup_rxfilter()
1583 val = RD4(sc, GENET_MDIO_CMD); in gen_miibus_readreg()
1614 val = RD4(sc, GENET_MDIO_CMD); in gen_miibus_writereg()
1617 val = RD4(sc, GENET_MDIO_CMD); in gen_miibus_writereg()
[all …]
/f-stack/freebsd/arm/allwinner/
H A Daw_thermal.c379 #define RD4(sc, reg) bus_read_4((sc)->res[0], (reg)) macro
423 WR4(sc, THS_INTS, RD4(sc, THS_INTS)); in aw_thermal_init()
424 WR4(sc, THS_INTC, RD4(sc, THS_INTC) | SHUT_INT_ALL | ALARM_INT_ALL); in aw_thermal_init()
427 WR4(sc, THS_CTRL2, RD4(sc, THS_CTRL2) | SENSOR_ENABLE_ALL); in aw_thermal_init()
437 val = RD4(sc, THS_DATA0 + (sensor * 4)); in aw_thermal_gettemp()
447 val = RD4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4)); in aw_thermal_getshut()
458 val = RD4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4)); in aw_thermal_setshut()
469 val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4)); in aw_thermal_gethyst()
480 val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4)); in aw_thermal_getalarm()
491 val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4)); in aw_thermal_setalarm()
[all …]
H A Daw_usb3phy.c108 #define RD4(res, o) bus_read_4(res, (o)) macro
125 val = RD4(sc->res, USB3PHY_PHY_EXTERNAL_CONTROL); in awusb3phy_phy_enable()
133 val = RD4(sc->res, USB3PHY_PIPE_CLOCK_CONTROL); in awusb3phy_phy_enable()
139 val = RD4(sc->res, USB3PHY_APP); in awusb3phy_phy_enable()
147 val = RD4(sc->res, USB3PHY_PHY_TUNE_HIGH); in awusb3phy_phy_enable()

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