Searched refs:R1 (Results 1 – 25 of 37) sorted by relevance
12
113 Pull up setings for 2 pull resistors, R0 and R1. User can115 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.116 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.117 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.118 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.124 Pull down settings for 2 pull resistors, R0 and R1. User can126 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.127 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.128 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.129 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
18 values R1 and R2 of the feedback voltage divider in ohms.22 0.4125 * (1 + R1/R2) V and 0.8 * (1 + R1/R2) V.25 0.725 * (1 + R1/R2) V. The ldo3 regulator is fixed to 1.8 V. The ldo1 standby
18 values R1 and R2 of the feedback voltage divider in ohms.22 0.3625 * (1 + R1/R2) V and 0.75 * (1 + R1/R2) V. Regulators bb-out and ldo123 have a fixed 0.8 V reference and thus output 0.8 * (1 + R1/R2) V. The ldo3
10 values R1 and R2 of the feedback voltage divider in kilo ohms.
285 /* VDD_SOC (1+R1/R2 = 1.635) */296 /* VDD_1P8 (1+R1/R2 = 2.505): ENET-PHY */307 /* VDD_ARM (1+R1/R2 = 1.635) */318 /* VDD_DDR (1+R1/R2 = 2.105) */329 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */339 /* VDD_HIGH (1+R1/R2 = 4.17) */
293 /* VDD_SOC (1+R1/R2 = 1.635) */304 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */315 /* VDD_ARM (1+R1/R2 = 1.635) */326 /* VDD_DDR (1+R1/R2 = 2.105) */337 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */347 /* VDD_HIGH (1+R1/R2 = 4.17) */
364 /* VDD_SOC (1+R1/R2 = 1.635) */375 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */386 /* VDD_ARM (1+R1/R2 = 1.635) */397 /* VDD_DDR (1+R1/R2 = 2.105) */408 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */426 /* VDD_HIGH (1+R1/R2 = 4.17) */
361 /* VDD_SOC (1+R1/R2 = 1.635) */372 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */383 /* VDD_ARM (1+R1/R2 = 1.635) */394 /* VDD_DDR (1+R1/R2 = 2.105) */405 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */423 /* VDD_HIGH (1+R1/R2 = 4.17) */
354 /* VDD_SOC (1+R1/R2 = 1.635) */365 /* VDD_DDR (1+R1/R2 = 2.105) */376 /* VDD_ARM (1+R1/R2 = 1.635) */387 /* VDD_3P3 (1+R1/R2 = 1.281) */398 /* VDD_1P8a (1+R1/R2 = 2.505): HDMI In core */416 /* VDD_HIGH (1+R1/R2 = 4.17) */
342 /* VDD_SOC (1+R1/R2 = 1.635) */353 /* VDD_DDR (1+R1/R2 = 2.105) */364 /* VDD_ARM (1+R1/R2 = 1.635) */375 /* VDD_3P3 (1+R1/R2 = 1.281) */386 /* VDD_1P8a (1+R1/R2 = 2.505): Analog Video Decoder */404 /* VDD_HIGH (1+R1/R2 = 4.17) */
405 /* VDD_SOC (1+R1/R2 = 1.635) */416 /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */427 /* VDD_ARM (1+R1/R2 = 1.635) */438 /* VDD_DDR (1+R1/R2 = 2.105) */449 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */459 /* VDD_HIGH (1+R1/R2 = 4.17) */
11 model = "Lamobo R1";
374 /* VDD_1P8 (1+R1/R2 = 2.505): Aud/eMMC/microSD/Touch */385 /* VDD_DDR (1+R1/R2 = 2.105) */396 /* VDD_ARM (1+R1/R2 = 1.635) */408 /* VDD_SOC (1+R1/R2 = 1.635) */420 /* VDD_1P0 (1+R1/R2 = 1.38): */430 /* VDD_HIGH (1+R1/R2 = 4.17) */
43 /* Orange Pi R1 is based on Orange Pi Zero design */47 model = "Xunlong Orange Pi R1";
487 /* VDD_DDR (1+R1/R2 = 2.105) */498 /* VDD_ARM (1+R1/R2 = 1.931) */510 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */521 /* VDD_1P0 (1+R1/R2 = 1.39): PCIe/ENET-PHY */539 /* VDD_HIGH (1+R1/R2 = 4.17) */
48 #define R1(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk(i)+0x5A827999+rol(v,5);w=rol(w,30); macro85 R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19); in SHA1Transform()
39 packet. Registers ``R1-R5`` are scratch registers56 and ``R1-R5`` were scratched.
32 * DMIC R1
33 * DMIC R1
40 * DMIC R1
44 * DMIC R1
47 * DMIC R1
50 * DMIC R1
48 * DMIC R1
22 For Juno R0 and Juno R1 refer to [1] for the