Searched refs:QCA955X_DDR_REG_FLUSH_GE1 (Results 1 – 2 of 2) sorted by relevance
209 #define QCA955X_DDR_REG_FLUSH_GE1 (AR71XX_APB_BASE + 0xa0) macro
218 ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_GE1); in qca955x_chip_ddr_flush()