Searched refs:QCA953X_PLL_DDR_CONFIG_REG (Results 1 – 2 of 2) sorted by relevance
65 #define QCA953X_PLL_DDR_CONFIG_REG (AR71XX_PLL_CPU_BASE + 0x04) macro
100 pll = ATH_READ_REG(QCA953X_PLL_DDR_CONFIG_REG); in qca953x_chip_detect_sys_frequency()