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Searched refs:Pad (Results 1 – 19 of 19) sorted by relevance

/f-stack/freebsd/contrib/device-tree/Bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.txt41 == Pad Control ==
51 Pad configurations are described with pin configuration nodes which
85 Pad configuration state example:
H A Dnvidia,tegra20-pmc.yaml244 This is a Pad configuration node. On Tegra SOCs a pad is a set of
/f-stack/freebsd/contrib/device-tree/Bindings/pinctrl/
H A Dfsl,imx27-pinctrl.txt91 and MUX_ID. They are structured as MX27_PAD_<Pad name>__<Signal name>. The names
H A Dnvidia,tegra114-pinmux.txt98 reg = <0x70000868 0x148 /* Pad control registers */
H A Dnvidia,tegra30-pinmux.txt110 reg = < 0x70000868 0xd0 /* Pad control registers */
H A Dnvidia,tegra124-pinmux.txt118 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
H A Dnvidia,tegra20-pinmux.txt124 0x70000868 0xa8 >; /* Pad control registers */
H A Dnvidia,tegra210-pinmux.txt148 reg = <0x0 0x700008d4 0x0 0x2a8>, /* Pad control registers */
/f-stack/freebsd/contrib/dev/acpica/common/
H A Ddmextern.c1761 char Pad[] = " *"; in AcpiDmUnresolvedWarning() local
1775 Format = Type ? Pad : NoPad; in AcpiDmUnresolvedWarning()
/f-stack/freebsd/contrib/device-tree/Bindings/memory-controllers/
H A Dnvidia,tegra30-emc.yaml60 Pad calibration interval in microseconds.
/f-stack/freebsd/contrib/device-tree/Bindings/net/
H A Dmicrel-ksz90x1.txt27 Device Tree Value Delay Pad Skew Register Value
/f-stack/freebsd/contrib/edk2/Include/Uefi/
H A DUefiInternalFormRepresentation.h144 UINT8 Pad[3]; member
/f-stack/freebsd/contrib/device-tree/src/arm/
H A Dtegra114.dtsi264 reg = <0x70000868 0x148>, /* Pad control registers */
H A Dtegra20.dtsi311 <0x70000868 0xa8>; /* Pad control registers */
H A Dtegra30.dtsi452 reg = <0x70000868 0x0d4>, /* Pad control registers */
H A Dtegra124.dtsi342 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
/f-stack/freebsd/contrib/device-tree/Bindings/phy/
H A Dnvidia,tegra124-xusb-padctl.txt71 Pad nodes:
/f-stack/freebsd/contrib/device-tree/src/arm64/nvidia/
H A Dtegra132.dtsi316 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
H A Dtegra210.dtsi542 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */