Searched refs:PLL_BASE_DIVN_SHIFT (Results 1 – 1 of 1) sorted by relevance
| /f-stack/freebsd/arm/nvidia/tegra124/ |
| H A D | tegra124_clk_pll.c | 74 #define PLL_BASE_DIVN_SHIFT 8 macro
498 *n = get_masked(val, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in get_divisors()
510 val = set_masked(val, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in set_divisors()
725 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in pll_set_std()
912 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in pllx_set_freq()
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