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Searched refs:PLLE_SS_CNTL (Results 1 – 4 of 4) sorted by relevance

/f-stack/freebsd/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c590 RD4(sc, PLLE_SS_CNTL, &reg); in plle_enable()
592 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
606 RD4(sc, PLLE_SS_CNTL, &reg); in plle_enable()
611 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
614 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
618 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
H A Dtegra124_car.h56 #define PLLE_SS_CNTL 0x068 macro
/f-stack/freebsd/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c783 RD4(sc, PLLE_SS_CNTL, &reg); in plle_enable()
785 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
797 RD4(sc, PLLE_SS_CNTL, &reg); in plle_enable()
806 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
809 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
813 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
H A Dtegra210_car.h60 #define PLLE_SS_CNTL 0x068 macro