Searched refs:PLL4 (Results 1 – 8 of 8) sorted by relevance
9 #define PLL4 0 macro
11 #define PLL4 0 macro
186 #define PLL4 179 macro
22 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for26 Note: the same PLL4 and PLL15 is used by the audio support on the CPB!29 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
17 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and22 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
837 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
3375 #define PLL4 0x1618c macro3386 while ( (OS_REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { in ar9300_get_pll3_sqsum_dvc()