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Searched refs:PLIST (Results 1 – 10 of 10) sorted by relevance

/f-stack/freebsd/arm64/rockchip/clk/
H A Drk3399_cru.c702 #define PLIST(_name) static const char *_name[] macro
703 PLIST(pll_src_p) = {"xin24m", "xin32k"};
711 PLIST(pll_src_cpll_gpll_p) = {"cpll", "gpll"};
733 PLIST(clk_cif_p) = {"clk_cifout_src", "xin24m"};
742 PLIST(aclk_perilp0_p) = { "cpll_aclk_perilp0_src",
745 PLIST(fclk_cm0s_p) = { "cpll_fclk_cm0s_src",
748 PLIST(hclk_perilp1_p) = { "cpll_hclk_perilp1_src",
754 PLIST(usbphy_480m_p) = { "clk_usbphy0_480m_src",
756 PLIST(aclk_gmac_p) = { "cpll_aclk_gmac_src",
758 PLIST(rmii_p) = { "clk_gmac", "clkin_gmac" };
[all …]
H A Drk3288_cru.c631 #define PLIST(_name) static const char *_name[] macro
632 PLIST(pll_src_p) = {"xin24m", "xin24m", "xin32k"};
633 PLIST(armclk_p)= {"apll_core", "gpll_core"};
634 PLIST(ddrphy_p) = {"dpll_ddr", "gpll_ddr"};
637 PLIST(cpll_gpll_p) = {"cpll", "gpll"};
645 PLIST(i2s_clkout_p) = {"i2s_pre", "xin12m"};
653 PLIST(vip_out_p) = {"vip_src", "xin24m"};
654 PLIST(mac_p) = {"mac_pll_src", "ext_gmac"};
655 PLIST(hsadcout_p) = {"hsadc_src", "ext_hsadc"};
656 PLIST(edp_24m_p) = {"ext_edp_24m", "xin24m"};
[all …]
/f-stack/freebsd/arm64/nvidia/tegra210/
H A Dtegra210_clk_per.c85 PLIST(mux_N_N_c_N_p_N_a) =
88 PLIST(mux_N_N_p_N_N_N_clkm) =
104 PLIST(mux_N_c2_c_c3_p_N_a) =
132 PLIST(mux_a_audiod1_p_clkm) =
135 PLIST(mux_a_audiod2_p_clkm) =
138 PLIST(mux_a_audiod3_p_clkm) =
145 PLIST(mux_a_clks_p_clkm_e) =
164 PLIST(mux_p_N_d_N_N_d2_clkm) =
213 PLIST(mux_p_m_d_a_c_d2_clkm) =
216 PLIST(mux_p_po3_clkm_clks_a) =
[all …]
H A Dtegra210_clk_super.c51 #define PLIST(x) static const char *x[] macro
63 PLIST(cclk_g_parents) = {
70 PLIST(cclk_lp_parents) = {
77 PLIST(sclk_parents) = {
H A Dtegra210_car.c65 #define PLIST(x) static const char *x[] macro
188 PLIST(mux_xusb_hs) = {"xusb_ss_div2", "pllU_60", "pc_xusb_ss" };
189 PLIST(mux_xusb_ssp) = {"xusb_ss", "osc_div_clk"};
H A Dtegra210_clk_pll.c145 #define PLIST(x) static const char *x[] macro
489 PLIST(mux_pll_srcs) = {"osc_div_clk", NULL, "pllP_out0", NULL}; /* FIXME */
490 PLIST(mux_plle_src1) = {"osc_div_clk", "pllP_out0"};
491 PLIST(mux_plle_src) = {"pllE_src1", "pllREFE_out0"};
/f-stack/freebsd/mips/ingenic/
H A Djz4780_clock.c125 #define PLIST(pnames...) \ macro
167 PLIST("cpumux"),
174 PLIST("cpumux"),
195 PLIST("ahb2_apb_mux"),
202 PLIST("ahb2_apb_mux"),
209 PLIST("sclk_a", "mpll"),
223 PLIST("sclk_a", "epll"),
230 PLIST("ext", "i2s_pll"),
258 PLIST("msc_mux"),
265 PLIST("msc_mux"),
[all …]
/f-stack/freebsd/arm/nvidia/tegra124/
H A Dtegra124_clk_per.c109 PLIST(mux_a_clks_p_clkm_e) =
112 PLIST(mux_a_c2_c_c3_p_N_clkm) =
116 PLIST(mux_m_c_p_a_c2_c3) =
132 PLIST(mux_m_c2_c_c3_p_N_a) =
139 PLIST(mux_p_N_c_N_N_N_clkm) =
142 PLIST(mux_p_N_c_N_m_N_clkm) =
145 PLIST(mux_p_c_c2_clkm) =
147 PLIST(mux_p_c2_c_c3_m) =
168 PLIST(mux_p_clkm_clks_E) =
170 PLIST(mux_p_m_d_a_c_d2_clkm) =
[all …]
H A Dtegra124_clk_super.c55 #define PLIST(x) static const char *x[] macro
69 PLIST(cclk_g_parents) = {
76 PLIST(cclk_lp_parents) = {
84 PLIST(sclk_parents) = {
H A Dtegra124_car.c64 #define PLIST(x) static const char *x[] macro
187 PLIST(mux_pll_srcs) = {"osc_div_clk", NULL, "pllP_out0", NULL}; /* FIXME */
188 PLIST(mux_plle_src1) = {"osc_div_clk", "pllP_out0"};
189 PLIST(mux_plle_src) = {"pllE_src1", "pllREFE_out"};
190 PLIST(mux_plld_out0_plld2_out0) = {"pllD_out0", "pllD2_out0"};
191 PLIST(mux_xusb_hs) = {"xusb_ss_div2", "pllU_60"};
192 PLIST(mux_xusb_ss) = {"pc_xusb_ss", "osc_div_clk"};