| /f-stack/freebsd/contrib/device-tree/Bindings/phy/ |
| H A D | phy-hisi-inno-usb2.txt | 1 Device tree bindings for HiSilicon INNO USB2 PHY
7 - reg: Should be the address space for PHY configuration register in peripheral
9 - clocks: The phandle and clock specifier pair for INNO USB2 PHY device
11 - resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
17 contains the PHY configuration register, and each device suppports up to 2 PHY
18 ports which are represented as child nodes of INNO USB2 PHY device.
20 Required properties for PHY port node:
21 - reg: The PHY port instance number.
22 - #phy-cells: Defined by generic PHY bindings. Must be 0.
23 - resets: The phandle and reset specifier pair for PHY port reset signal.
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| H A D | phy-bindings.txt | 2 information about PHY subsystem refer to Documentation/driver-api/phy/phy.rst
4 PHY device node
8 #phy-cells: Number of cells in a PHY specifier; The meaning of all those
9 cells is defined by the binding for the phy node. The PHY
11 PHY.
14 phy-supply: Phandle to a regulator that provides power to the PHY. This
15 regulator will be managed during the PHY power on/off sequence.
29 That node describes an IP block (PHY provider) that implements 2 different PHYs.
33 PHY user node
37 phys : the phandle for the PHY device (used by the PHY subsystem; not to be
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| H A D | phy-mtk-ufs.txt | 1 MediaTek Universal Flash Storage (UFS) M-PHY binding
4 UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
5 Each UFS M-PHY node should have its own node.
7 To bind UFS M-PHY with UFS host controller, the controller node should
8 contain a phandle reference to UFS M-PHY node.
10 Required properties for UFS M-PHY nodes:
14 - reg : Address and length of the UFS M-PHY register set.
21 "mp": M-PHY core control clock.
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| H A D | brcm,stingray-usb-phy.txt | 1 Broadcom Stingray USB PHY
5 - "brcm,sr-usb-combo-phy" is combo PHY has two PHYs, one SS and one HS.
6 - "brcm,sr-usb-hs-phy" is a single HS PHY.
7 - reg: offset and length of the PHY blocks registers
10 the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties
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| H A D | phy-stm32-usbphyc.txt | 1 STMicroelectronics STM32 USB HS PHY controller
3 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
4 switch. It controls PHY configuration and status, and the UTMI+ switch that
5 selects either OTG or HOST controller for the second PHY port. It also sets
11 |_ PHY port#1 _________________ HOST controller
14 |_ PHY port#2 ----| |________________
41 - phy-supply: phandle to the regulator providing 3V3 power to the PHY,
43 - vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
44 - vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
45 - #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY
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| H A D | samsung-phy.txt | 14 In case of exynos5433 compatible PHY:
21 the PHY specifier identifies the PHY and its meaning is as follows:
27 supports additional fifth PHY:
30 Samsung Exynos SoC series Display Port PHY
41 Samsung S5P/Exynos SoC series USB PHY
59 PHY module
64 The first phandle argument in the PHY specifier identifies the PHY, its
90 Then the PHY can be used in other nodes such as:
100 Samsung SATA PHY Controller
170 PHY id, which is interpreted as follows:
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| H A D | lantiq,vrx200-pcie-phy.yaml | 7 title: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings
15 description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
27 - description: PHY module clock
37 - description: exclusive PHY reset line
38 - description: shared reset line between the PCIe PHY and PCIe controller
51 description: the offset of the endian registers for this PHY instance in the RCU syscon
55 description: the mask to set the PDI (PHY) registers for this PHY instance to big endian
58 description: Configures the PDI (PHY) registers in big-endian mode
62 description: Configures the PDI (PHY) registers in big-endian mode
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| H A D | ti-phy.txt | 1 TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
3 OMAP CONTROL PHY
11 e.g. USB3 PHY and SATA PHY on OMAP5.
14 e.g. PCIE PHY in DRA7x
30 OMAP USB2 PHY
34 Should be "ti,dra7x-usb2" for the 1st instance of USB2 PHY on
50 the PHY.
54 module and the register offset to power on/off the PHY.
67 TI PIPE3 PHY
100 the PHY.
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| H A D | allwinner,sun8i-h3-usb-phy.yaml | 7 title: Allwinner H3 USB PHY Device Tree Bindings
22 - description: PHY Control registers
23 - description: PHY PMU0 registers
24 - description: PHY PMU1 registers
25 - description: PHY PMU2 registers
26 - description: PHY PMU3 registers
38 - description: USB OTG PHY bus clock
39 - description: USB Host 0 PHY bus clock
40 - description: USB Host 1 PHY bus clock
41 - description: USB Host 2 PHY bus clock
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| H A D | phy-mvebu-utmi.txt | 1 MVEBU A3700 UTMI PHY
4 USB2 UTMI+ PHY controllers can be found on the following Marvell MVEBU SoCs:
10 different UTMI PHY.
15 * "marvell,a3700-utmi-host-phy" for the PHY connected to
17 * "marvell,a3700-utmi-otg-phy" for the PHY connected to
19 - reg: PHY IP register range.
22 controller and the PHY.
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| H A D | phy-cadence-torrent.yaml | 7 title: Cadence Torrent SD0801 PHY binding for DisplayPort
10 This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
32 PHY reference clock. Must contain an entry in clock-names.
41 - description: Offset of the Torrent PHY configuration registers.
42 - description: Offset of the DPTX PHY configuration registers.
54 Torrent PHY reset.
61 Each group of PHY lanes with a single master lane should be represented as a sub-node.
78 Specifies the type of PHY for which the group of PHY lanes is used.
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| H A D | keystone-usb-phy.txt | 1 TI Keystone USB PHY
9 The main purpose of this PHY driver is to enable the USB PHY reference clock
10 gate on the Keystone SOC for both the USB2 and USB3 PHY. Otherwise it is just
11 an NOP PHY driver. Hence this node is referenced as both the usb2 and usb3
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| H A D | allwinner,sun8i-r40-usb-phy.yaml | 7 title: Allwinner R40 USB PHY Device Tree Bindings
22 - description: PHY Control registers
23 - description: PHY PMU0 registers
24 - description: PHY PMU1 registers
25 - description: PHY PMU2 registers
36 - description: USB OTG PHY bus clock
37 - description: USB Host 0 PHY bus clock
38 - description: USB Host 1 PHY bus clock
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| H A D | nvidia,tegra20-usb-phy.txt | 1 Tegra SOC USB PHY
3 The device node for Tegra SOC USB PHY:
11 - The PHY's own register set.
13 - The register set of the PHY containing the UTMI pad control registers.
18 - reg: The clock needed to access the PHY's own registers. This is the
24 - ulpi-link: The clock Tegra provides to the ULPI PHY (usually pad DAP_MCLK2
31 - usb: The PHY's own reset signal.
32 - utmi-pads: The reset of the PHY containing the chip-wide UTMI pad control
36 - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
38 Required PHY timing params for utmi phy, for all chips:
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| H A D | brcm,ns2-drd-phy.txt | 1 BROADCOM NORTHSTAR2 USB2 (DUAL ROLE DEVICE) PHY
5 - reg: offset and length of the NS2 PHY related registers.
10 crmu-ctrl - for CRMU core vdd, PHY and PHY PLL reset
16 Refer to phy/phy-bindings.txt for the generic PHY binding properties
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| H A D | rockchip-usb-phy.txt | 1 ROCKCHIP USB2 PHY
16 Each PHY should be represented as a sub-node.
21 - reg: PHY configure reg address offset in GRF
22 "0x320" - for PHY attach to OTG controller
23 "0x334" - for PHY attach to HOST0 controller
24 "0x348" - for PHY attach to HOST1 controller
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| H A D | socionext,uniphier-usb2-phy.yaml | 7 title: Socionext UniPhier USB2 PHY
10 This describes the devicetree bindings for PHY interface built into
13 controller doesn't include its own High-Speed PHY. This needs to specify
14 USB2 PHY instead of USB3 HS-PHY.
41 The ID number for the PHY
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| H A D | brcm,sr-pcie-phy.txt | 1 Broadcom Stingray PCIe PHY
8 - #phy-cells: Must be 1, denotes the PHY index
11 PHY index goes from 0 to 7
13 For the internal PAXC based root complex, PHY index is always 8
34 /* users of the PCIe PHY */
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| H A D | phy-tegra194-p2u.txt | 3 Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
6 interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe
15 Required properties for PHY port node:
16 - #phy-cells: Defined by generic PHY bindings. Must be 0.
18 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
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| /f-stack/freebsd/contrib/device-tree/Bindings/usb/ |
| H A D | usb-nop-xceiv.txt | 1 USB NOP PHY
8 - clocks: phandle to the PHY clock. Use as per Documentation/devicetree
14 - clock-frequency: the clock frequency (in Hz) that the PHY clock must
17 - vcc-supply: phandle to the regulator that provides power to the PHY.
40 hsusb1_phy is a NOP USB PHY device that gets its clock from an oscillator
41 and expects that clock to be configured to 19.2MHz by the NOP PHY driver.
42 hsusb1_vcc_regulator provides power to the PHY and GPIO 7 controls RESET.
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| /f-stack/freebsd/contrib/device-tree/Bindings/net/ |
| H A D | ethernet-phy.yaml | 7 title: Ethernet PHY Generic Binding
57 The ID number for the PHY.
78 Maximum PHY supported speed in Mbits / seconds.
83 If set, indicates the PHY device does not correctly release
90 If set, indicates the PHY will swap the TX/RX lanes to
133 If set, indicates that the PHY is integrated into the same
135 should be configured to ensure the integrated PHY is
137 should be configured so that the external PHY is used.
148 The GPIO phandle and specifier for the PHY reset signal.
169 present then the PHY applies the RX delay.
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| H A D | micrel.txt | 1 Micrel PHY properties.
20 See the respective PHY datasheet for the mode values.
28 Note that this option in only needed for certain PHY revisions with a
39 - micrel,fiber-mode: If present the PHY is configured to operate in fiber mode
42 by the FXEN boot strapping pin. It can't be determined from the PHY
43 registers whether the PHY is in fiber mode, so this boolean device tree
46 In fiber mode, auto-negotiation is disabled and the PHY can only work in
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| H A D | nxp,tja11xx.yaml | 7 title: NXP TJA11xx PHY
24 Some packages have multiple PHYs. Secondary PHY should be defines as
25 subnode of the first (parent) PHY.
32 The ID number for the child PHY. Should be +1 of parent PHY.
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| /f-stack/freebsd/contrib/device-tree/Bindings/ufs/ |
| H A D | ufs-qcom.txt | 1 * Qualcomm Technologies Inc Universal Flash Storage (UFS) PHY
3 UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro.
4 Each UFS PHY node should have its own node.
6 To bind UFS PHY with UFS host controller, the controller node should
7 contain a phandle reference to UFS PHY node.
15 - reg : should contain PHY register address space (mandatory),
19 - vdda-phy-supply : phandle to main PHY supply for analog domain
20 - vdda-pll-supply : phandle to PHY PLL and Power-Gen block power supply
32 - resets : specifies the PHY reset in the UFS controller
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| /f-stack/freebsd/contrib/device-tree/Bindings/mmc/ |
| H A D | marvell,xenon-sdhci.txt | 7 clock and PHY.
30 PHY PAD Voltage Control register.
46 To select eMMC 5.1 PHY, set:
49 To select eMMC 5.0 PHY, set:
53 Please note that this property only presents the type of PHY.
59 Set PHY ZNR value.
60 Only available for eMMC PHY.
65 Set PHY ZPR value.
66 Only available for eMMC PHY.
81 If this property is selected, transfers will bypass PHY.
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