| /f-stack/freebsd/contrib/device-tree/src/powerpc/fsl/ |
| H A D | mpc8641_hpcn_36b.dts | 134 /* IDSEL 0x11 func 0 - PCI slot 1 */
140 /* IDSEL 0x11 func 1 - PCI slot 1 */
146 /* IDSEL 0x11 func 2 - PCI slot 1 */
152 /* IDSEL 0x11 func 3 - PCI slot 1 */
158 /* IDSEL 0x11 func 4 - PCI slot 1 */
164 /* IDSEL 0x11 func 5 - PCI slot 1 */
170 /* IDSEL 0x11 func 6 - PCI slot 1 */
176 /* IDSEL 0x11 func 7 - PCI slot 1 */
182 /* IDSEL 0x12 func 0 - PCI slot 2 */
188 /* IDSEL 0x12 func 1 - PCI slot 2 */
[all …]
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| H A D | mpc8641_hpcn.dts | 167 /* IDSEL 0x11 func 0 - PCI slot 1 */
173 /* IDSEL 0x11 func 1 - PCI slot 1 */
179 /* IDSEL 0x11 func 2 - PCI slot 1 */
185 /* IDSEL 0x11 func 3 - PCI slot 1 */
191 /* IDSEL 0x11 func 4 - PCI slot 1 */
197 /* IDSEL 0x11 func 5 - PCI slot 1 */
203 /* IDSEL 0x11 func 6 - PCI slot 1 */
209 /* IDSEL 0x11 func 7 - PCI slot 1 */
215 /* IDSEL 0x12 func 0 - PCI slot 2 */
221 /* IDSEL 0x12 func 1 - PCI slot 2 */
[all …]
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| H A D | mpc8572ds.dtsi | 249 /* IDSEL 0x11 func 0 - PCI slot 1 */
255 /* IDSEL 0x11 func 1 - PCI slot 1 */
261 /* IDSEL 0x11 func 2 - PCI slot 1 */
267 /* IDSEL 0x11 func 3 - PCI slot 1 */
273 /* IDSEL 0x11 func 4 - PCI slot 1 */
279 /* IDSEL 0x11 func 5 - PCI slot 1 */
285 /* IDSEL 0x11 func 6 - PCI slot 1 */
291 /* IDSEL 0x11 func 7 - PCI slot 1 */
297 /* IDSEL 0x12 func 0 - PCI slot 2 */
303 /* IDSEL 0x12 func 1 - PCI slot 2 */
[all …]
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| /f-stack/freebsd/contrib/device-tree/Bindings/net/wireless/ |
| H A D | qca,ath9k.txt | 4 node is expected to be specified as a child node of the PCI controller to
8 - compatible: For PCI and PCIe devices this should be an identifier following
9 the format as defined in "PCI Bus Binding to Open Firmware"
11 where VVVV is the PCI vendor ID and DDDD is PCI device ID.
12 Typically QCA's PCI vendor ID 168c is used while the PCI device
41 In this example, the node is defined as child node of the PCI controller:
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| /f-stack/freebsd/contrib/device-tree/Bindings/pci/ |
| H A D | ralink,rt3883-pci.txt | 1 * Mediatek/Ralink RT3883 PCI controller
29 interrupt controller and the PCI host bridge.
48 b) PCI host bridge:
63 - bus-range: PCI bus numbers covered
65 - ranges: specifies the ranges for the PCI memory and I/O regions
68 - interrupt-map: standard PCI properties to define the mapping of the
69 PCI interface to interrupt numbers.
71 The PCI host bridge node might have additional sub-nodes representing
72 the onboard PCI devices/PCI slots. Each such sub-node must have the
80 If a given sub-node represents a PCI bridge it must have following
[all …]
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| H A D | 83xx-512x-pci.txt | 1 * Freescale 83xx and 512x PCI bridges
3 Freescale 83xx and 512x SOCs include the same PCI bridge core.
7 The first is for the internal PCI bridge registers
8 The second is for the PCI config space access registers
14 /* IDSEL 0x0E -mini PCI */
20 /* IDSEL 0x0F - PCI slot */
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| H A D | faraday,ftpci100.txt | 1 Faraday Technology FTPCI100 PCI Host Bridge
3 This PCI bridge is found inside that Cortina Systems Gemini SoC platform and
5 plain and dual PCI. The plain version embeds a cascading interrupt controller
9 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
35 PCI clock (PCICLK). If these are not present, they are assumed to be
36 hard-wired enabled and always on. The PCI clock will be 33 or 66 MHz.
38 clock and "PCICLK" for the PCI-side clock.
88 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, /* PCI A */
89 <26 IRQ_TYPE_LEVEL_HIGH>, /* PCI B */
90 <27 IRQ_TYPE_LEVEL_HIGH>, /* PCI C */
[all …]
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| H A D | fsl,pci.txt | 1 * Bus Enumeration by Freescale PCI-X Agent
3 Typically any Freescale PCI-X bridge hardware strapped into Agent mode
5 all mezzanines to be PCI-X Agents, but one per system may still
8 The property defined below will allow a PCI-X bridge to be used for bus
17 /* PCI-X bridge known to be PrPMC Monarch */
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| H A D | pci-keystone.txt | 3 Keystone PCI host Controller is based on the Synopsys DesignWare PCI
23 interrupts: GIC interrupt lines connected to PCI MSI interrupt lines
31 PCI in either RC mode or EP mode.
63 phys: phandle to generic Keystone SerDes PHY for PCI
64 phy-names: name of the generic Keystone SerDes PHY for PCI
65 - If boot loader already does PCI link establishment, then phys and
69 DesignWare DT Properties not applicable for Keystone PCI
93 PCI in either RC mode or EP mode.
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| H A D | pci.txt | 1 PCI bus bridges have standardized Device Tree bindings:
3 PCI Bus Binding to: IEEE Std 1275-1994
15 If present this property assigns a fixed PCI domain number to a host bridge,
22 If present this property specifies PCI gen for link capability. Host
36 PCI-PCI Bridge properties
47 Identifies the PCI-PCI bridge. As defined in the IEEE Std 1275-1994
|
| H A D | mobiveil-pcie.txt | 27 - bus-range: PCI bus numbers covered
35 interrupt-map: standard PCI properties to define the mapping of the
36 PCI interface to interrupt numbers.
37 - ranges: ranges for the PCI memory regions (I/O space region is not
39 Please refer to the standard PCI bus binding document for a more
|
| H A D | xilinx-pcie.txt | 13 interrupt-map: standard PCI properties to define the mapping of the
14 PCI interface to interrupt numbers.
15 - ranges: ranges for the PCI memory regions (I/O space region is not
17 Please refer to the standard PCI bus binding document for a more
21 - bus-range: PCI bus numbers covered
|
| H A D | pci-iommu.txt | 2 relationship between PCI(e) devices and IOMMU(s).
4 Each PCI(e) device under a root complex is uniquely identified by its Requester
16 IOMMUs may distinguish PCI devices through sideband data derived from the
17 Requester ID. While a given PCI device can only master through one IOMMU, a
22 and a mechanism is required to map from a PCI device to its IOMMU and sideband
29 PCI root complex
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| /f-stack/freebsd/contrib/device-tree/Bindings/virtio/ |
| H A D | iommu.txt | 1 * virtio IOMMU PCI device
3 When virtio-iommu uses the PCI transport, its programming interface is
4 discovered dynamically by the PCI probing infrastructure. However the
6 masters. Therefore, the PCI root complex that hosts the virtio-iommu
12 - reg: PCI address of the IOMMU. As defined in the PCI Bus
42 * The IOMMU manages all functions in this PCI domain except
|
| /f-stack/dpdk/doc/guides/rel_notes/ |
| H A D | release_17_02.rst | 436 * Host interface: PCI Express 3.0 x8
442 * Host interface: PCI Express 3.0 x8
448 * Host interface: PCI Express 3.0 x8
454 * Host interface: PCI Express 3.0 x8
460 * Host interface: PCI Express 3.0 x8
466 * Host interface: PCI Express 3.0 x8
478 * Host interface: PCI Express 3.0 x8
484 * Host interface: PCI Express 3.0 x8
508 * Host interface: PCI Express 3.0 x8
514 * Host interface: PCI Express 3.0 x8
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| H A D | release_18_08.rst | 418 * Host interface: PCI Express 3.0 x8
424 * Host interface: PCI Express 3.0 x8
430 * Host interface: PCI Express 3.0 x8
436 * Host interface: PCI Express 3.0 x8
442 * Host interface: PCI Express 3.0 x8
448 * Host interface: PCI Express 3.0 x8
460 * Host interface: PCI Express 3.0 x8
466 * Host interface: PCI Express 3.0 x8
491 * Host interface: PCI Express 3.0 x8
497 * Host interface: PCI Express 3.0 x8
[all …]
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| H A D | release_18_02.rst | 451 * Host interface: PCI Express 3.0 x8
457 * Host interface: PCI Express 3.0 x8
463 * Host interface: PCI Express 3.0 x8
469 * Host interface: PCI Express 3.0 x8
475 * Host interface: PCI Express 3.0 x8
481 * Host interface: PCI Express 3.0 x8
493 * Host interface: PCI Express 3.0 x8
499 * Host interface: PCI Express 3.0 x8
524 * Host interface: PCI Express 3.0 x8
530 * Host interface: PCI Express 3.0 x8
[all …]
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| H A D | release_19_02.rst | 511 * Host interface: PCI Express 3.0 x8
517 * Host interface: PCI Express 3.0 x8
523 * Host interface: PCI Express 3.0 x8
529 * Host interface: PCI Express 3.0 x8
535 * Host interface: PCI Express 3.0 x8
541 * Host interface: PCI Express 3.0 x8
553 * Host interface: PCI Express 3.0 x8
559 * Host interface: PCI Express 3.0 x8
584 * Host interface: PCI Express 3.0 x8
590 * Host interface: PCI Express 3.0 x8
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| H A D | release_20_08.rst | 195 * Added mlx5 PCI layer to share a PCI device among multiple PMDs.
522 * Host interface: PCI Express 3.0 x8
528 * Host interface: PCI Express 3.0 x8
534 * Host interface: PCI Express 3.0 x8
540 * Host interface: PCI Express 3.0 x8
546 * Host interface: PCI Express 3.0 x16
552 * Host interface: PCI Express 3.0 x16
558 * Host interface: PCI Express 3.0 x16
578 * Host interface: PCI Express 3.0 x16
643 * Host interface: PCI Express 3.0 x8
[all …]
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| H A D | release_17_05.rst | 667 * Host interface: PCI Express 3.0 x8
673 * Host interface: PCI Express 3.0 x8
679 * Host interface: PCI Express 3.0 x8
685 * Host interface: PCI Express 3.0 x8
691 * Host interface: PCI Express 3.0 x8
697 * Host interface: PCI Express 3.0 x8
709 * Host interface: PCI Express 3.0 x8
715 * Host interface: PCI Express 3.0 x8
739 * Host interface: PCI Express 3.0 x8
745 * Host interface: PCI Express 3.0 x8
[all …]
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| /f-stack/dpdk/doc/guides/prog_guide/ |
| H A D | rawdev.rst | 75 (PCI) | (PCI) (PCI) (PCI)
78 * It is assumed above that DrvB is a PCI type driver which registers itself
79 with PCI Bus
80 * Thereafter, when the PCI scan is done, during probe DrvB would match the
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| /f-stack/freebsd/contrib/device-tree/Bindings/x86/ |
| H A D | ce4100.txt | 47 The PCI node
49 This node describes the PCI bus on the SoC. Its property should be
56 to contain at least the reg property containing the PCI bus address and
57 compatible property according to "PCI Bus Binding Revision 2.1".
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| /f-stack/freebsd/contrib/device-tree/Bindings/i2c/ |
| H A D | i2c-pxa-pci-ce4100.txt | 4 CE4100 has one PCI device which is described as the I2C-Controller. This
5 PCI device has three PCI-bars, each bar contains a complete I2C
8 The driver is probed via the PCI-ID and is gathering the information of
10 Grant Likely recommended to use the ranges property to map the PCI-Bar
|
| /f-stack/dpdk/doc/guides/nics/ |
| H A D | bnx2x.rst | 185 #. PCI Passthrough:
203 EAL: PCI device 0000:84:00.0 on NUMA socket 1
205 EAL: PCI memory mapped at 0x7f14f6fe5000
206 EAL: PCI memory mapped at 0x7f14f67e5000
207 EAL: PCI memory mapped at 0x7f15fbd9b000
208 EAL: PCI device 0000:84:00.1 on NUMA socket 1
210 EAL: PCI memory mapped at 0x7f14f5fe5000
211 EAL: PCI memory mapped at 0x7f14f57e5000
212 EAL: PCI memory mapped at 0x7f15fbd4f000
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| H A D | nfp.rst | 86 2) Then try the PCI name:
113 DPDK apps work with ports, and a port is usually a PF or a VF PCI device.
114 However, with the NFP PF multiport there is just one PF PCI device. Supporting
117 PCI ports.
120 suffix added to the PCI ID: wwww:xx:yy.z_port_n. For example, a PF with PCI ID
159 current NFP PCI device detected by the system:
166 whose PCI system identity is "0000:03:00.0":
178 Two new PCI devices should appear in the output of the above command. The
180 Depending on the modules loaded at this point the new PCI devices may be
|