Searched refs:N_PORTS (Results 1 – 4 of 4) sorted by relevance
19 struct rte_ring *rings_rx[N_PORTS];20 struct rte_ring *rings_tx[N_PORTS];23 uint32_t port_in_id[N_PORTS];24 uint32_t port_out_id[N_PORTS];26 uint32_t table_id[N_PORTS*2];71 for (i = 0; i < N_PORTS; i++) in app_free_resources()98 for (i = 0; i < N_PORTS; i++) { in app_init_rings()114 for (i = 0; i < N_PORTS; i++) { in app_init_rings()
29 #define N_PORTS 2 macro117 extern struct rte_ring *rings_rx[N_PORTS];118 extern struct rte_ring *rings_tx[N_PORTS];120 extern uint32_t port_in_id[N_PORTS];121 extern uint32_t port_out_id[N_PORTS];123 extern uint32_t table_id[N_PORTS*2];
253 for (i = 0; i < N_PORTS; i++) { in setup_pipeline()279 for (i = 0; i < N_PORTS; i++) { in setup_pipeline()303 for (i = 0; i < N_PORTS; i++) { in setup_pipeline()325 for (i = 0; i < N_PORTS; i++) in setup_pipeline()334 for (i = 0; i < N_PORTS; i++) { in setup_pipeline()386 for (i = 0; i < N_PORTS ; i++) in setup_pipeline()415 for (i = 0; i < N_PORTS; i++) in test_pipeline_single_filter()429 for (i = 0; i < N_PORTS; i++) in test_pipeline_single_filter()430 for (j = 0; j < N_PORTS; j++) { in test_pipeline_single_filter()452 for (i = 0; i < N_PORTS; i++) in test_pipeline_single_filter()[all …]
353 for (i = 0; i < N_PORTS; i++) { in setup_acl_pipeline()379 for (i = 0; i < N_PORTS; i++) { in setup_acl_pipeline()401 for (i = 0; i < N_PORTS; i++) { in setup_acl_pipeline()442 for (i = 0; i < N_PORTS; i++) { in setup_acl_pipeline()453 for (i = 0; i < N_PORTS; i++) { in setup_acl_pipeline()497 for (i = 0; i < N_PORTS; i++) { in setup_acl_pipeline()533 for (i = 0; i < N_PORTS; i++) { in setup_acl_pipeline()623 for (i = 0; i < N_PORTS ; i++) in setup_acl_pipeline()647 for (i = 0; i < N_PORTS; i++) { in test_pipeline_single_filter()675 for (i = 0; i< N_PORTS; i++) in test_pipeline_single_filter()[all …]