1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2019 Marvell International Ltd. 3 */ 4 5 #ifndef __OTX2_NPA_HW_H__ 6 #define __OTX2_NPA_HW_H__ 7 8 /* Register offsets */ 9 10 #define NPA_AF_BLK_RST (0x0ull) 11 #define NPA_AF_CONST (0x10ull) 12 #define NPA_AF_CONST1 (0x18ull) 13 #define NPA_AF_LF_RST (0x20ull) 14 #define NPA_AF_GEN_CFG (0x30ull) 15 #define NPA_AF_NDC_CFG (0x40ull) 16 #define NPA_AF_NDC_SYNC (0x50ull) 17 #define NPA_AF_INP_CTL (0xd0ull) 18 #define NPA_AF_ACTIVE_CYCLES_PC (0xf0ull) 19 #define NPA_AF_AVG_DELAY (0x100ull) 20 #define NPA_AF_GEN_INT (0x140ull) 21 #define NPA_AF_GEN_INT_W1S (0x148ull) 22 #define NPA_AF_GEN_INT_ENA_W1S (0x150ull) 23 #define NPA_AF_GEN_INT_ENA_W1C (0x158ull) 24 #define NPA_AF_RVU_INT (0x160ull) 25 #define NPA_AF_RVU_INT_W1S (0x168ull) 26 #define NPA_AF_RVU_INT_ENA_W1S (0x170ull) 27 #define NPA_AF_RVU_INT_ENA_W1C (0x178ull) 28 #define NPA_AF_ERR_INT (0x180ull) 29 #define NPA_AF_ERR_INT_W1S (0x188ull) 30 #define NPA_AF_ERR_INT_ENA_W1S (0x190ull) 31 #define NPA_AF_ERR_INT_ENA_W1C (0x198ull) 32 #define NPA_AF_RAS (0x1a0ull) 33 #define NPA_AF_RAS_W1S (0x1a8ull) 34 #define NPA_AF_RAS_ENA_W1S (0x1b0ull) 35 #define NPA_AF_RAS_ENA_W1C (0x1b8ull) 36 #define NPA_AF_AQ_CFG (0x600ull) 37 #define NPA_AF_AQ_BASE (0x610ull) 38 #define NPA_AF_AQ_STATUS (0x620ull) 39 #define NPA_AF_AQ_DOOR (0x630ull) 40 #define NPA_AF_AQ_DONE_WAIT (0x640ull) 41 #define NPA_AF_AQ_DONE (0x650ull) 42 #define NPA_AF_AQ_DONE_ACK (0x660ull) 43 #define NPA_AF_AQ_DONE_TIMER (0x670ull) 44 #define NPA_AF_AQ_DONE_INT (0x680ull) 45 #define NPA_AF_AQ_DONE_ENA_W1S (0x690ull) 46 #define NPA_AF_AQ_DONE_ENA_W1C (0x698ull) 47 #define NPA_AF_LFX_AURAS_CFG(a) (0x4000ull | (uint64_t)(a) << 18) 48 #define NPA_AF_LFX_LOC_AURAS_BASE(a) (0x4010ull | (uint64_t)(a) << 18) 49 #define NPA_AF_LFX_QINTS_CFG(a) (0x4100ull | (uint64_t)(a) << 18) 50 #define NPA_AF_LFX_QINTS_BASE(a) (0x4110ull | (uint64_t)(a) << 18) 51 #define NPA_PRIV_AF_INT_CFG (0x10000ull) 52 #define NPA_PRIV_LFX_CFG(a) (0x10010ull | (uint64_t)(a) << 8) 53 #define NPA_PRIV_LFX_INT_CFG(a) (0x10020ull | (uint64_t)(a) << 8) 54 #define NPA_AF_RVU_LF_CFG_DEBUG (0x10030ull) 55 #define NPA_AF_DTX_FILTER_CTL (0x10040ull) 56 57 #define NPA_LF_AURA_OP_ALLOCX(a) (0x10ull | (uint64_t)(a) << 3) 58 #define NPA_LF_AURA_OP_FREE0 (0x20ull) 59 #define NPA_LF_AURA_OP_FREE1 (0x28ull) 60 #define NPA_LF_AURA_OP_CNT (0x30ull) 61 #define NPA_LF_AURA_OP_LIMIT (0x50ull) 62 #define NPA_LF_AURA_OP_INT (0x60ull) 63 #define NPA_LF_AURA_OP_THRESH (0x70ull) 64 #define NPA_LF_POOL_OP_PC (0x100ull) 65 #define NPA_LF_POOL_OP_AVAILABLE (0x110ull) 66 #define NPA_LF_POOL_OP_PTR_START0 (0x120ull) 67 #define NPA_LF_POOL_OP_PTR_START1 (0x128ull) 68 #define NPA_LF_POOL_OP_PTR_END0 (0x130ull) 69 #define NPA_LF_POOL_OP_PTR_END1 (0x138ull) 70 #define NPA_LF_POOL_OP_INT (0x160ull) 71 #define NPA_LF_POOL_OP_THRESH (0x170ull) 72 #define NPA_LF_ERR_INT (0x200ull) 73 #define NPA_LF_ERR_INT_W1S (0x208ull) 74 #define NPA_LF_ERR_INT_ENA_W1C (0x210ull) 75 #define NPA_LF_ERR_INT_ENA_W1S (0x218ull) 76 #define NPA_LF_RAS (0x220ull) 77 #define NPA_LF_RAS_W1S (0x228ull) 78 #define NPA_LF_RAS_ENA_W1C (0x230ull) 79 #define NPA_LF_RAS_ENA_W1S (0x238ull) 80 #define NPA_LF_QINTX_CNT(a) (0x300ull | (uint64_t)(a) << 12) 81 #define NPA_LF_QINTX_INT(a) (0x310ull | (uint64_t)(a) << 12) 82 #define NPA_LF_QINTX_ENA_W1S(a) (0x320ull | (uint64_t)(a) << 12) 83 #define NPA_LF_QINTX_ENA_W1C(a) (0x330ull | (uint64_t)(a) << 12) 84 85 86 /* Enum offsets */ 87 88 #define NPA_AQ_COMP_NOTDONE (0x0ull) 89 #define NPA_AQ_COMP_GOOD (0x1ull) 90 #define NPA_AQ_COMP_SWERR (0x2ull) 91 #define NPA_AQ_COMP_CTX_POISON (0x3ull) 92 #define NPA_AQ_COMP_CTX_FAULT (0x4ull) 93 #define NPA_AQ_COMP_LOCKERR (0x5ull) 94 95 #define NPA_AF_INT_VEC_RVU (0x0ull) 96 #define NPA_AF_INT_VEC_GEN (0x1ull) 97 #define NPA_AF_INT_VEC_AQ_DONE (0x2ull) 98 #define NPA_AF_INT_VEC_AF_ERR (0x3ull) 99 #define NPA_AF_INT_VEC_POISON (0x4ull) 100 101 #define NPA_AQ_INSTOP_NOP (0x0ull) 102 #define NPA_AQ_INSTOP_INIT (0x1ull) 103 #define NPA_AQ_INSTOP_WRITE (0x2ull) 104 #define NPA_AQ_INSTOP_READ (0x3ull) 105 #define NPA_AQ_INSTOP_LOCK (0x4ull) 106 #define NPA_AQ_INSTOP_UNLOCK (0x5ull) 107 108 #define NPA_AQ_CTYPE_AURA (0x0ull) 109 #define NPA_AQ_CTYPE_POOL (0x1ull) 110 111 #define NPA_BPINTF_NIX0_RX (0x0ull) 112 #define NPA_BPINTF_NIX1_RX (0x1ull) 113 114 #define NPA_AURA_ERR_INT_AURA_FREE_UNDER (0x0ull) 115 #define NPA_AURA_ERR_INT_AURA_ADD_OVER (0x1ull) 116 #define NPA_AURA_ERR_INT_AURA_ADD_UNDER (0x2ull) 117 #define NPA_AURA_ERR_INT_POOL_DIS (0x3ull) 118 #define NPA_AURA_ERR_INT_R4 (0x4ull) 119 #define NPA_AURA_ERR_INT_R5 (0x5ull) 120 #define NPA_AURA_ERR_INT_R6 (0x6ull) 121 #define NPA_AURA_ERR_INT_R7 (0x7ull) 122 123 #define NPA_LF_INT_VEC_ERR_INT (0x40ull) 124 #define NPA_LF_INT_VEC_POISON (0x41ull) 125 #define NPA_LF_INT_VEC_QINT_END (0x3full) 126 #define NPA_LF_INT_VEC_QINT_START (0x0ull) 127 128 #define NPA_INPQ_SSO (0x4ull) 129 #define NPA_INPQ_TIM (0x5ull) 130 #define NPA_INPQ_DPI (0x6ull) 131 #define NPA_INPQ_AURA_OP (0xeull) 132 #define NPA_INPQ_INTERNAL_RSV (0xfull) 133 #define NPA_INPQ_NIX0_RX (0x0ull) 134 #define NPA_INPQ_NIX1_RX (0x2ull) 135 #define NPA_INPQ_NIX0_TX (0x1ull) 136 #define NPA_INPQ_NIX1_TX (0x3ull) 137 #define NPA_INPQ_R_END (0xdull) 138 #define NPA_INPQ_R_START (0x7ull) 139 140 #define NPA_POOL_ERR_INT_OVFLS (0x0ull) 141 #define NPA_POOL_ERR_INT_RANGE (0x1ull) 142 #define NPA_POOL_ERR_INT_PERR (0x2ull) 143 #define NPA_POOL_ERR_INT_R3 (0x3ull) 144 #define NPA_POOL_ERR_INT_R4 (0x4ull) 145 #define NPA_POOL_ERR_INT_R5 (0x5ull) 146 #define NPA_POOL_ERR_INT_R6 (0x6ull) 147 #define NPA_POOL_ERR_INT_R7 (0x7ull) 148 149 #define NPA_NDC0_PORT_AURA0 (0x0ull) 150 #define NPA_NDC0_PORT_AURA1 (0x1ull) 151 #define NPA_NDC0_PORT_POOL0 (0x2ull) 152 #define NPA_NDC0_PORT_POOL1 (0x3ull) 153 #define NPA_NDC0_PORT_STACK0 (0x4ull) 154 #define NPA_NDC0_PORT_STACK1 (0x5ull) 155 156 #define NPA_LF_ERR_INT_AURA_DIS (0x0ull) 157 #define NPA_LF_ERR_INT_AURA_OOR (0x1ull) 158 #define NPA_LF_ERR_INT_AURA_FAULT (0xcull) 159 #define NPA_LF_ERR_INT_POOL_FAULT (0xdull) 160 #define NPA_LF_ERR_INT_STACK_FAULT (0xeull) 161 #define NPA_LF_ERR_INT_QINT_FAULT (0xfull) 162 163 /* Structures definitions */ 164 165 /* NPA admin queue instruction structure */ 166 struct npa_aq_inst_s { 167 uint64_t op : 4; 168 uint64_t ctype : 4; 169 uint64_t lf : 9; 170 uint64_t rsvd_23_17 : 7; 171 uint64_t cindex : 20; 172 uint64_t rsvd_62_44 : 19; 173 uint64_t doneint : 1; 174 uint64_t res_addr : 64; /* W1 */ 175 }; 176 177 /* NPA admin queue result structure */ 178 struct npa_aq_res_s { 179 uint64_t op : 4; 180 uint64_t ctype : 4; 181 uint64_t compcode : 8; 182 uint64_t doneint : 1; 183 uint64_t rsvd_63_17 : 47; 184 uint64_t rsvd_127_64 : 64; /* W1 */ 185 }; 186 187 /* NPA aura operation write data structure */ 188 struct npa_aura_op_wdata_s { 189 uint64_t aura : 20; 190 uint64_t rsvd_62_20 : 43; 191 uint64_t drop : 1; 192 }; 193 194 /* NPA aura context structure */ 195 struct npa_aura_s { 196 uint64_t pool_addr : 64;/* W0 */ 197 uint64_t ena : 1; 198 uint64_t rsvd_66_65 : 2; 199 uint64_t pool_caching : 1; 200 uint64_t pool_way_mask : 16; 201 uint64_t avg_con : 9; 202 uint64_t rsvd_93 : 1; 203 uint64_t pool_drop_ena : 1; 204 uint64_t aura_drop_ena : 1; 205 uint64_t bp_ena : 2; 206 uint64_t rsvd_103_98 : 6; 207 uint64_t aura_drop : 8; 208 uint64_t shift : 6; 209 uint64_t rsvd_119_118 : 2; 210 uint64_t avg_level : 8; 211 uint64_t count : 36; 212 uint64_t rsvd_167_164 : 4; 213 uint64_t nix0_bpid : 9; 214 uint64_t rsvd_179_177 : 3; 215 uint64_t nix1_bpid : 9; 216 uint64_t rsvd_191_189 : 3; 217 uint64_t limit : 36; 218 uint64_t rsvd_231_228 : 4; 219 uint64_t bp : 8; 220 uint64_t rsvd_243_240 : 4; 221 uint64_t fc_ena : 1; 222 uint64_t fc_up_crossing : 1; 223 uint64_t fc_stype : 2; 224 uint64_t fc_hyst_bits : 4; 225 uint64_t rsvd_255_252 : 4; 226 uint64_t fc_addr : 64;/* W4 */ 227 uint64_t pool_drop : 8; 228 uint64_t update_time : 16; 229 uint64_t err_int : 8; 230 uint64_t err_int_ena : 8; 231 uint64_t thresh_int : 1; 232 uint64_t thresh_int_ena : 1; 233 uint64_t thresh_up : 1; 234 uint64_t rsvd_363 : 1; 235 uint64_t thresh_qint_idx : 7; 236 uint64_t rsvd_371 : 1; 237 uint64_t err_qint_idx : 7; 238 uint64_t rsvd_383_379 : 5; 239 uint64_t thresh : 36; 240 uint64_t rsvd_447_420 : 28; 241 uint64_t rsvd_511_448 : 64;/* W7 */ 242 }; 243 244 /* NPA pool context structure */ 245 struct npa_pool_s { 246 uint64_t stack_base : 64;/* W0 */ 247 uint64_t ena : 1; 248 uint64_t nat_align : 1; 249 uint64_t rsvd_67_66 : 2; 250 uint64_t stack_caching : 1; 251 uint64_t rsvd_71_69 : 3; 252 uint64_t stack_way_mask : 16; 253 uint64_t buf_offset : 12; 254 uint64_t rsvd_103_100 : 4; 255 uint64_t buf_size : 11; 256 uint64_t rsvd_127_115 : 13; 257 uint64_t stack_max_pages : 32; 258 uint64_t stack_pages : 32; 259 uint64_t op_pc : 48; 260 uint64_t rsvd_255_240 : 16; 261 uint64_t stack_offset : 4; 262 uint64_t rsvd_263_260 : 4; 263 uint64_t shift : 6; 264 uint64_t rsvd_271_270 : 2; 265 uint64_t avg_level : 8; 266 uint64_t avg_con : 9; 267 uint64_t fc_ena : 1; 268 uint64_t fc_stype : 2; 269 uint64_t fc_hyst_bits : 4; 270 uint64_t fc_up_crossing : 1; 271 uint64_t rsvd_299_297 : 3; 272 uint64_t update_time : 16; 273 uint64_t rsvd_319_316 : 4; 274 uint64_t fc_addr : 64;/* W5 */ 275 uint64_t ptr_start : 64;/* W6 */ 276 uint64_t ptr_end : 64;/* W7 */ 277 uint64_t rsvd_535_512 : 24; 278 uint64_t err_int : 8; 279 uint64_t err_int_ena : 8; 280 uint64_t thresh_int : 1; 281 uint64_t thresh_int_ena : 1; 282 uint64_t thresh_up : 1; 283 uint64_t rsvd_555 : 1; 284 uint64_t thresh_qint_idx : 7; 285 uint64_t rsvd_563 : 1; 286 uint64_t err_qint_idx : 7; 287 uint64_t rsvd_575_571 : 5; 288 uint64_t thresh : 36; 289 uint64_t rsvd_639_612 : 28; 290 uint64_t rsvd_703_640 : 64;/* W10 */ 291 uint64_t rsvd_767_704 : 64;/* W11 */ 292 uint64_t rsvd_831_768 : 64;/* W12 */ 293 uint64_t rsvd_895_832 : 64;/* W13 */ 294 uint64_t rsvd_959_896 : 64;/* W14 */ 295 uint64_t rsvd_1023_960 : 64;/* W15 */ 296 }; 297 298 /* NPA queue interrupt context hardware structure */ 299 struct npa_qint_hw_s { 300 uint32_t count : 22; 301 uint32_t rsvd_30_22 : 9; 302 uint32_t ena : 1; 303 }; 304 305 #endif /* __OTX2_NPA_HW_H__ */ 306