1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2018 Netronome Systems, Inc.
3 * All rights reserved.
4 */
5
6 /*
7 * vim:shiftwidth=8:noexpandtab
8 *
9 * @file dpdk/pmd/nfp_net_pmd.h
10 *
11 * Netronome NFP_NET PMD driver
12 */
13
14 #ifndef _NFP_NET_PMD_H_
15 #define _NFP_NET_PMD_H_
16
17 #define NFP_NET_PMD_VERSION "0.1"
18 #define PCI_VENDOR_ID_NETRONOME 0x19ee
19 #define PCI_DEVICE_ID_NFP4000_PF_NIC 0x4000
20 #define PCI_DEVICE_ID_NFP6000_PF_NIC 0x6000
21 #define PCI_DEVICE_ID_NFP6000_VF_NIC 0x6003
22
23 /* Forward declaration */
24 struct nfp_net_adapter;
25
26 /*
27 * The maximum number of descriptors is limited by design as
28 * DPDK uses uint16_t variables for these values
29 */
30 #define NFP_NET_MAX_TX_DESC (32 * 1024)
31 #define NFP_NET_MIN_TX_DESC 64
32
33 #define NFP_NET_MAX_RX_DESC (32 * 1024)
34 #define NFP_NET_MIN_RX_DESC 64
35
36 /* Descriptor alignment */
37 #define NFP_ALIGN_RING_DESC 128
38
39 #define NFP_TX_MAX_SEG UINT8_MAX
40 #define NFP_TX_MAX_MTU_SEG 8
41
42 /* Bar allocation */
43 #define NFP_NET_CRTL_BAR 0
44 #define NFP_NET_TX_BAR 2
45 #define NFP_NET_RX_BAR 2
46 #define NFP_QCP_QUEUE_AREA_SZ 0x80000
47
48 /* Macros for accessing the Queue Controller Peripheral 'CSRs' */
49 #define NFP_QCP_QUEUE_OFF(_x) ((_x) * 0x800)
50 #define NFP_QCP_QUEUE_ADD_RPTR 0x0000
51 #define NFP_QCP_QUEUE_ADD_WPTR 0x0004
52 #define NFP_QCP_QUEUE_STS_LO 0x0008
53 #define NFP_QCP_QUEUE_STS_LO_READPTR_mask (0x3ffff)
54 #define NFP_QCP_QUEUE_STS_HI 0x000c
55 #define NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask (0x3ffff)
56
57 /* Interrupt definitions */
58 #define NFP_NET_IRQ_LSC_IDX 0
59
60 /* Default values for RX/TX configuration */
61 #define DEFAULT_RX_FREE_THRESH 32
62 #define DEFAULT_RX_PTHRESH 8
63 #define DEFAULT_RX_HTHRESH 8
64 #define DEFAULT_RX_WTHRESH 0
65
66 #define DEFAULT_TX_RS_THRESH 32
67 #define DEFAULT_TX_FREE_THRESH 32
68 #define DEFAULT_TX_PTHRESH 32
69 #define DEFAULT_TX_HTHRESH 0
70 #define DEFAULT_TX_WTHRESH 0
71 #define DEFAULT_TX_RSBIT_THRESH 32
72
73 /* Alignment for dma zones */
74 #define NFP_MEMZONE_ALIGN 128
75
76 /*
77 * This is used by the reconfig protocol. It sets the maximum time waiting in
78 * milliseconds before a reconfig timeout happens.
79 */
80 #define NFP_NET_POLL_TIMEOUT 5000
81
82 #define NFP_QCP_QUEUE_ADDR_SZ (0x800)
83
84 #define NFP_NET_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
85 #define NFP_NET_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
86
87 /* Version number helper defines */
88 #define NFD_CFG_CLASS_VER_msk 0xff
89 #define NFD_CFG_CLASS_VER_shf 24
90 #define NFD_CFG_CLASS_VER(x) (((x) & 0xff) << 24)
91 #define NFD_CFG_CLASS_VER_of(x) (((x) >> 24) & 0xff)
92 #define NFD_CFG_CLASS_TYPE_msk 0xff
93 #define NFD_CFG_CLASS_TYPE_shf 16
94 #define NFD_CFG_CLASS_TYPE(x) (((x) & 0xff) << 16)
95 #define NFD_CFG_CLASS_TYPE_of(x) (((x) >> 16) & 0xff)
96 #define NFD_CFG_MAJOR_VERSION_msk 0xff
97 #define NFD_CFG_MAJOR_VERSION_shf 8
98 #define NFD_CFG_MAJOR_VERSION(x) (((x) & 0xff) << 8)
99 #define NFD_CFG_MAJOR_VERSION_of(x) (((x) >> 8) & 0xff)
100 #define NFD_CFG_MINOR_VERSION_msk 0xff
101 #define NFD_CFG_MINOR_VERSION_shf 0
102 #define NFD_CFG_MINOR_VERSION(x) (((x) & 0xff) << 0)
103 #define NFD_CFG_MINOR_VERSION_of(x) (((x) >> 0) & 0xff)
104
105 #include <linux/types.h>
106 #include <rte_io.h>
107
nn_readb(volatile const void * addr)108 static inline uint8_t nn_readb(volatile const void *addr)
109 {
110 return rte_read8(addr);
111 }
112
nn_writeb(uint8_t val,volatile void * addr)113 static inline void nn_writeb(uint8_t val, volatile void *addr)
114 {
115 rte_write8(val, addr);
116 }
117
nn_readl(volatile const void * addr)118 static inline uint32_t nn_readl(volatile const void *addr)
119 {
120 return rte_read32(addr);
121 }
122
nn_writel(uint32_t val,volatile void * addr)123 static inline void nn_writel(uint32_t val, volatile void *addr)
124 {
125 rte_write32(val, addr);
126 }
127
nn_writew(uint16_t val,volatile void * addr)128 static inline void nn_writew(uint16_t val, volatile void *addr)
129 {
130 rte_write16(val, addr);
131 }
132
nn_readq(volatile void * addr)133 static inline uint64_t nn_readq(volatile void *addr)
134 {
135 const volatile uint32_t *p = addr;
136 uint32_t low, high;
137
138 high = nn_readl((volatile const void *)(p + 1));
139 low = nn_readl((volatile const void *)p);
140
141 return low + ((uint64_t)high << 32);
142 }
143
nn_writeq(uint64_t val,volatile void * addr)144 static inline void nn_writeq(uint64_t val, volatile void *addr)
145 {
146 nn_writel(val >> 32, (volatile char *)addr + 4);
147 nn_writel(val, addr);
148 }
149
150 /* TX descriptor format */
151 #define PCIE_DESC_TX_EOP (1 << 7)
152 #define PCIE_DESC_TX_OFFSET_MASK (0x7f)
153
154 /* Flags in the host TX descriptor */
155 #define PCIE_DESC_TX_CSUM (1 << 7)
156 #define PCIE_DESC_TX_IP4_CSUM (1 << 6)
157 #define PCIE_DESC_TX_TCP_CSUM (1 << 5)
158 #define PCIE_DESC_TX_UDP_CSUM (1 << 4)
159 #define PCIE_DESC_TX_VLAN (1 << 3)
160 #define PCIE_DESC_TX_LSO (1 << 2)
161 #define PCIE_DESC_TX_ENCAP_NONE (0)
162 #define PCIE_DESC_TX_ENCAP_VXLAN (1 << 1)
163 #define PCIE_DESC_TX_ENCAP_GRE (1 << 0)
164
165 struct nfp_net_tx_desc {
166 union {
167 struct {
168 uint8_t dma_addr_hi; /* High bits of host buf address */
169 __le16 dma_len; /* Length to DMA for this desc */
170 uint8_t offset_eop; /* Offset in buf where pkt starts +
171 * highest bit is eop flag.
172 */
173 __le32 dma_addr_lo; /* Low 32bit of host buf addr */
174
175 __le16 mss; /* MSS to be used for LSO */
176 uint8_t lso_hdrlen; /* LSO, where the data starts */
177 uint8_t flags; /* TX Flags, see @PCIE_DESC_TX_* */
178
179 union {
180 struct {
181 /*
182 * L3 and L4 header offsets required
183 * for TSOv2
184 */
185 uint8_t l3_offset;
186 uint8_t l4_offset;
187 };
188 __le16 vlan; /* VLAN tag to add if indicated */
189 };
190 __le16 data_len; /* Length of frame + meta data */
191 } __rte_packed;
192 __le32 vals[4];
193 };
194 };
195
196 struct nfp_net_txq {
197 struct nfp_net_hw *hw; /* Backpointer to nfp_net structure */
198
199 /*
200 * Queue information: @qidx is the queue index from Linux's
201 * perspective. @tx_qcidx is the index of the Queue
202 * Controller Peripheral queue relative to the TX queue BAR.
203 * @cnt is the size of the queue in number of
204 * descriptors. @qcp_q is a pointer to the base of the queue
205 * structure on the NFP
206 */
207 uint8_t *qcp_q;
208
209 /*
210 * Read and Write pointers. @wr_p and @rd_p are host side pointer,
211 * they are free running and have little relation to the QCP pointers *
212 * @qcp_rd_p is a local copy queue controller peripheral read pointer
213 */
214
215 uint32_t wr_p;
216 uint32_t rd_p;
217
218 uint32_t tx_count;
219
220 uint32_t tx_free_thresh;
221
222 /*
223 * For each descriptor keep a reference to the mbuf and
224 * DMA address used until completion is signalled.
225 */
226 struct {
227 struct rte_mbuf *mbuf;
228 } *txbufs;
229
230 /*
231 * Information about the host side queue location. @txds is
232 * the virtual address for the queue, @dma is the DMA address
233 * of the queue and @size is the size in bytes for the queue
234 * (needed for free)
235 */
236 struct nfp_net_tx_desc *txds;
237
238 /*
239 * At this point 48 bytes have been used for all the fields in the
240 * TX critical path. We have room for 8 bytes and still all placed
241 * in a cache line. We are not using the threshold values below but
242 * if we need to, we can add the most used in the remaining bytes.
243 */
244 uint32_t tx_rs_thresh; /* not used by now. Future? */
245 uint32_t tx_pthresh; /* not used by now. Future? */
246 uint32_t tx_hthresh; /* not used by now. Future? */
247 uint32_t tx_wthresh; /* not used by now. Future? */
248 uint16_t port_id;
249 int qidx;
250 int tx_qcidx;
251 __le64 dma;
252 } __rte_aligned(64);
253
254 /* RX and freelist descriptor format */
255 #define PCIE_DESC_RX_DD (1 << 7)
256 #define PCIE_DESC_RX_META_LEN_MASK (0x7f)
257
258 /* Flags in the RX descriptor */
259 #define PCIE_DESC_RX_RSS (1 << 15)
260 #define PCIE_DESC_RX_I_IP4_CSUM (1 << 14)
261 #define PCIE_DESC_RX_I_IP4_CSUM_OK (1 << 13)
262 #define PCIE_DESC_RX_I_TCP_CSUM (1 << 12)
263 #define PCIE_DESC_RX_I_TCP_CSUM_OK (1 << 11)
264 #define PCIE_DESC_RX_I_UDP_CSUM (1 << 10)
265 #define PCIE_DESC_RX_I_UDP_CSUM_OK (1 << 9)
266 #define PCIE_DESC_RX_SPARE (1 << 8)
267 #define PCIE_DESC_RX_EOP (1 << 7)
268 #define PCIE_DESC_RX_IP4_CSUM (1 << 6)
269 #define PCIE_DESC_RX_IP4_CSUM_OK (1 << 5)
270 #define PCIE_DESC_RX_TCP_CSUM (1 << 4)
271 #define PCIE_DESC_RX_TCP_CSUM_OK (1 << 3)
272 #define PCIE_DESC_RX_UDP_CSUM (1 << 2)
273 #define PCIE_DESC_RX_UDP_CSUM_OK (1 << 1)
274 #define PCIE_DESC_RX_VLAN (1 << 0)
275
276 #define PCIE_DESC_RX_L4_CSUM_OK (PCIE_DESC_RX_TCP_CSUM_OK | \
277 PCIE_DESC_RX_UDP_CSUM_OK)
278 struct nfp_net_rx_desc {
279 union {
280 /* Freelist descriptor */
281 struct {
282 uint8_t dma_addr_hi;
283 __le16 spare;
284 uint8_t dd;
285
286 __le32 dma_addr_lo;
287 } __rte_packed fld;
288
289 /* RX descriptor */
290 struct {
291 __le16 data_len;
292 uint8_t reserved;
293 uint8_t meta_len_dd;
294
295 __le16 flags;
296 __le16 vlan;
297 } __rte_packed rxd;
298
299 __le32 vals[2];
300 };
301 };
302
303 struct nfp_net_rx_buff {
304 struct rte_mbuf *mbuf;
305 };
306
307 struct nfp_net_rxq {
308 struct nfp_net_hw *hw; /* Backpointer to nfp_net structure */
309
310 /*
311 * @qcp_fl and @qcp_rx are pointers to the base addresses of the
312 * freelist and RX queue controller peripheral queue structures on the
313 * NFP
314 */
315 uint8_t *qcp_fl;
316 uint8_t *qcp_rx;
317
318 /*
319 * Read and Write pointers. @wr_p and @rd_p are host side
320 * pointer, they are free running and have little relation to
321 * the QCP pointers. @wr_p is where the driver adds new
322 * freelist descriptors and @rd_p is where the driver start
323 * reading descriptors for newly arrive packets from.
324 */
325 uint32_t rd_p;
326
327 /*
328 * For each buffer placed on the freelist, record the
329 * associated SKB
330 */
331 struct nfp_net_rx_buff *rxbufs;
332
333 /*
334 * Information about the host side queue location. @rxds is
335 * the virtual address for the queue
336 */
337 struct nfp_net_rx_desc *rxds;
338
339 /*
340 * The mempool is created by the user specifying a mbuf size.
341 * We save here the reference of the mempool needed in the RX
342 * path and the mbuf size for checking received packets can be
343 * safely copied to the mbuf using the NFP_NET_RX_OFFSET
344 */
345 struct rte_mempool *mem_pool;
346 uint16_t mbuf_size;
347
348 /*
349 * Next two fields are used for giving more free descriptors
350 * to the NFP
351 */
352 uint16_t rx_free_thresh;
353 uint16_t nb_rx_hold;
354
355 /* the size of the queue in number of descriptors */
356 uint16_t rx_count;
357
358 /*
359 * Fields above this point fit in a single cache line and are all used
360 * in the RX critical path. Fields below this point are just used
361 * during queue configuration or not used at all (yet)
362 */
363
364 /* referencing dev->data->port_id */
365 uint16_t port_id;
366
367 uint8_t crc_len; /* Not used by now */
368 uint8_t drop_en; /* Not used by now */
369
370 /* DMA address of the queue */
371 __le64 dma;
372
373 /*
374 * Queue information: @qidx is the queue index from Linux's
375 * perspective. @fl_qcidx is the index of the Queue
376 * Controller peripheral queue relative to the RX queue BAR
377 * used for the freelist and @rx_qcidx is the Queue Controller
378 * Peripheral index for the RX queue.
379 */
380 int qidx;
381 int fl_qcidx;
382 int rx_qcidx;
383 } __rte_aligned(64);
384
385 struct nfp_net_hw {
386 /* Info from the firmware */
387 uint32_t ver;
388 uint32_t cap;
389 uint32_t max_mtu;
390 uint32_t mtu;
391 uint32_t rx_offset;
392
393 /* Current values for control */
394 uint32_t ctrl;
395
396 uint8_t *ctrl_bar;
397 uint8_t *tx_bar;
398 uint8_t *rx_bar;
399
400 int stride_rx;
401 int stride_tx;
402
403 uint8_t *qcp_cfg;
404 rte_spinlock_t reconfig_lock;
405
406 uint32_t max_tx_queues;
407 uint32_t max_rx_queues;
408 uint16_t flbufsz;
409 uint16_t device_id;
410 uint16_t vendor_id;
411 uint16_t subsystem_device_id;
412 uint16_t subsystem_vendor_id;
413 #if defined(DSTQ_SELECTION)
414 #if DSTQ_SELECTION
415 uint16_t device_function;
416 #endif
417 #endif
418
419 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
420
421 /* Records starting point for counters */
422 struct rte_eth_stats eth_stats_base;
423
424 struct nfp_cpp *cpp;
425 struct nfp_cpp_area *ctrl_area;
426 struct nfp_cpp_area *hwqueues_area;
427 struct nfp_cpp_area *msix_area;
428
429 uint8_t *hw_queues;
430 uint8_t is_pf;
431 uint8_t pf_port_idx;
432 uint8_t pf_multiport_enabled;
433 uint8_t total_ports;
434
435 union eth_table_entry *eth_table;
436
437 struct nfp_hwinfo *hwinfo;
438 struct nfp_rtsym_table *sym_tbl;
439 uint32_t nfp_cpp_service_id;
440 };
441
442 struct nfp_net_adapter {
443 struct nfp_net_hw hw;
444 };
445
446 #define NFP_NET_DEV_PRIVATE_TO_HW(adapter)\
447 (&((struct nfp_net_adapter *)adapter)->hw)
448
449 #endif /* _NFP_NET_PMD_H_ */
450 /*
451 * Local variables:
452 * c-file-style: "Linux"
453 * indent-tabs-mode: t
454 * End:
455 */
456