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Searched refs:NAE_REG (Results 1 – 8 of 8) sorted by relevance

/f-stack/freebsd/mips/nlm/hal/
H A Dnae.h46 #define NAE_RX_CONFIG NAE_REG(7, 0, 0x10)
64 #define NAE_RX_UCORE_CFG NAE_REG(7, 0, 0x23)
78 #define NAE_TEST NAE_REG(7, 0, 0x5f)
80 #define NAE_BIU_CFG NAE_REG(7, 0, 0x61)
82 #define NAE_RX_DSBL_ECC NAE_REG(7, 0, 0x63)
127 #define NAE_L3CTABLE0 NAE_REG(7, 0, 0x230)
157 #define NAE_TX_CONFIG NAE_REG(7, 0, 0x11)
226 #define NAE_TX_EL0 NAE_REG(7, 0, 0x328)
227 #define NAE_TX_EL1 NAE_REG(7, 0, 0x329)
228 #define NAE_EIC0 NAE_REG(7, 0, 0x32a)
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H A Dxaui.h40 #define XAUI_CONFIG0(block) NAE_REG(block, 4, 0x00)
41 #define XAUI_CONFIG1(block) NAE_REG(block, 4, 0x01)
42 #define XAUI_CONFIG2(block) NAE_REG(block, 4, 0x02)
43 #define XAUI_CONFIG3(block) NAE_REG(block, 4, 0x03)
49 #define XAUI_REVISION_LVL(block) NAE_REG(block, 4, 0x0b)
55 #define XAUI_STATS_MLR(block) NAE_REG(block, 4, 0x1f)
56 #define XAUI_STATS_TR64(block) NAE_REG(block, 4, 0x20)
60 #define XAUI_STATS_TR1K(block) NAE_REG(block, 4, 0x24)
63 #define XAUI_STATS_RBYT(block) NAE_REG(block, 4, 0x27)
64 #define XAUI_STATS_RPKT(block) NAE_REG(block, 4, 0x28)
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H A Dsgmii.h42 #define SGMII_MAC_CONF1(block, i) NAE_REG(block, i, 0x00)
43 #define SGMII_MAC_CONF2(block, i) NAE_REG(block, i, 0x01)
44 #define SGMII_IPG_IFG(block, i) NAE_REG(block, i, 0x02)
45 #define SGMII_HLF_DUP(block, i) NAE_REG(block, i, 0x03)
46 #define SGMII_MAX_FRAME(block, i) NAE_REG(block, i, 0x04)
47 #define SGMII_TEST(block, i) NAE_REG(block, i, 0x07)
48 #define SGMII_MIIM_CONF(block, i) NAE_REG(block, i, 0x08)
49 #define SGMII_MIIM_CMD(block, i) NAE_REG(block, i, 0x09)
53 #define SGMII_MIIM_IND(block, i) NAE_REG(block, i, 0x0d)
54 #define SGMII_IO_CTRL(block, i) NAE_REG(block, i, 0x0e)
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H A Dinterlaken.h41 #define ILK_TX_CONTROL(block) NAE_REG(block, 5, 0x00)
44 #define ILK_RX_CTRL(block) NAE_REG(block, 5, 0x03)
45 #define ILK_RX_STATUS1(block) NAE_REG(block, 5, 0x04)
46 #define ILK_RX_STATUS2(block) NAE_REG(block, 5, 0x05)
48 #define ILK_STATUS3(block) NAE_REG(block, 5, 0x07)
49 #define ILK_RX_FC_TMAP0(block) NAE_REG(block, 5, 0x08)
50 #define ILK_RX_FC_TMAP1(block) NAE_REG(block, 5, 0x09)
51 #define ILK_RX_FC_TMAP2(block) NAE_REG(block, 5, 0x0a)
52 #define ILK_RX_FC_TMAP3(block) NAE_REG(block, 5, 0x0b)
65 #define ILK_MID_COUNT0(block) NAE_REG(block, 5, 0x18)
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/f-stack/freebsd/mips/nlm/dev/net/
H A Dmdio.c64 NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4))); in nlm_int_gmac_mdio_read()
67 NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus*4)), in nlm_int_gmac_mdio_read()
72 NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)), in nlm_int_gmac_mdio_read()
77 NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)), in nlm_int_gmac_mdio_read()
87 NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)), in nlm_int_gmac_mdio_read()
117 NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus*4)), in nlm_int_gmac_mdio_write()
193 NAE_REG(block, intf_type, in nlm_gmac_mdio_read()
207 NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), in nlm_gmac_mdio_read()
211 NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)), in nlm_gmac_mdio_read()
254 NAE_REG(block, intf_type, in nlm_gmac_mdio_write()
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H A Dxaui.c67 NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_0_1)); in nlm_xaui_pcs_init()
77 NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_0_1), in nlm_xaui_pcs_init()
83 NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_2_3)); in nlm_xaui_pcs_init()
93 NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_2_3), in nlm_xaui_pcs_init()
120 reg = NAE_REG(block, PHY, lane_ctrl - 4); in nlm_xaui_pcs_init()
H A Dnae.c393 NAE_REG(block, PHY, lane_ctrl)); in xlp_ax_nae_lane_reset_txpll()
399 NAE_REG(block, PHY, lane_ctrl), val); in xlp_ax_nae_lane_reset_txpll()
415 NAE_REG(block, PHY, lane_ctrl), in xlp_ax_nae_lane_reset_txpll()
424 NAE_REG(block, PHY, lane_ctrl))) & in xlp_ax_nae_lane_reset_txpll()
431 NAE_REG(block, PHY, lane_ctrl), in xlp_ax_nae_lane_reset_txpll()
442 NAE_REG(block, PHY, lane_ctrl), in xlp_ax_nae_lane_reset_txpll()
473 NAE_REG(block, PHY, lane_ctrl)); in xlp_nae_lane_reset_txpll()
482 NAE_REG(block, PHY, lane_ctrl), val); in xlp_nae_lane_reset_txpll()
485 NAE_REG(block, PHY, lane_ctrl)); in xlp_nae_lane_reset_txpll()
488 NAE_REG(block, PHY, lane_ctrl), val); in xlp_nae_lane_reset_txpll()
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H A Dsgmii.c56 nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF1), data1); in nlm_configure_sgmii_interface()
61 nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF2), data2); in nlm_configure_sgmii_interface()
65 nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF1), data1); in nlm_configure_sgmii_interface()