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Searched refs:MUX (Results 1 – 25 of 26) sorted by relevance

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/f-stack/freebsd/arm64/qoriq/clk/
H A Dlx2160a_clkgen.c119 #define MUX(_id1, _id2, cname, plist, o) \ macro
132 MUX(QORIQ_TYPE_CMUX, 0, "cg-cmux0", cmuxa_plist, 0x70000);
134 MUX(QORIQ_TYPE_CMUX, 1, "cg-cmux1", cmuxa_plist, 0x70020);
136 MUX(QORIQ_TYPE_CMUX, 2, "cg-cmux2", cmuxa_plist, 0x70040);
138 MUX(QORIQ_TYPE_CMUX, 3, "cg-cmux3", cmuxa_plist, 0x70060);
140 MUX(QORIQ_TYPE_CMUX, 4, "cg-cmux4", cmuxb_plist, 0x70080);
142 MUX(QORIQ_TYPE_CMUX, 5, "cg-cmux5", cmuxb_plist, 0x700A0);
144 MUX(QORIQ_TYPE_CMUX, 6, "cg-cmux6", cmuxb_plist, 0x700C0);
146 MUX(QORIQ_TYPE_CMUX, 7, "cg-cmux7", cmuxb_plist, 0x700E0);
/f-stack/freebsd/arm64/freescale/imx/
H A Dimx8mq_ccm.c138 MUX(IMX8MQ_ARM_PLL_REF_SEL, "arm_pll_ref_sel", pll_ref_p, 0, 0x28, 16, 2),
139 MUX(IMX8MQ_GPU_PLL_REF_SEL, "gpu_pll_ref_sel", pll_ref_p, 0, 0x18, 16, 2),
140 MUX(IMX8MQ_VPU_PLL_REF_SEL, "vpu_pll_ref_sel", pll_ref_p, 0, 0x20, 16, 2),
141 MUX(IMX8MQ_AUDIO_PLL1_REF_SEL, "audio_pll1_ref_sel", pll_ref_p, 0, 0x0, 16, 2),
142 MUX(IMX8MQ_AUDIO_PLL2_REF_SEL, "audio_pll2_ref_sel", pll_ref_p, 0, 0x8, 16, 2),
143 MUX(IMX8MQ_VIDEO_PLL1_REF_SEL, "video_pll1_ref_sel", pll_ref_p, 0, 0x10, 16, 2),
144 MUX(IMX8MQ_SYS3_PLL1_REF_SEL, "sys3_pll1_ref_sel", pll_ref_p, 0, 0x48, 0, 2),
145 MUX(IMX8MQ_DRAM_PLL1_REF_SEL, "dram_pll1_ref_sel", pll_ref_p, 0, 0x60, 0, 2),
163 MUX(IMX8MQ_ARM_PLL_BYPASS, "arm_pll_bypass", arm_pll_bypass_p, 0, 0x28, 14, 1),
164 MUX(IMX8MQ_GPU_PLL_BYPASS, "gpu_pll_bypass", gpu_pll_bypass_p, 0, 0x18, 14, 1),
[all …]
H A Dimx_ccm_clk.h79 #define MUX(_id, _name, _pn, _f, _mo, _ms, _mw) \ macro
/f-stack/freebsd/arm64/rockchip/clk/
H A Drk3399_cru.c881 MUX(0, "upll", pll_src_24m_usbphy480m_p, 0,
887 MUX(0, "clk_usbphy_480m", usbphy_480m_p, 0,
985 MUX(0, "clk_i2sout_c", i2sout_p, 0,
987 MUX(0, "clk_i2sout_src", i2sch_p, 0,
993 MUX(0, "clk_spdif_mux", spdif_p, 0,
1003 MUX(SCLK_UART0, "clk_uart0", uart0_p, 0,
1009 MUX(SCLK_UART1, "clk_uart1", uart1_p, 0,
1015 MUX(SCLK_UART2, "clk_uart2", uart2_p, 0,
1021 MUX(SCLK_UART3, "clk_uart3", uart3_p, 0,
1090 MUX(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, 0,
[all …]
H A Drk3288_cru.c722 MUX(0, "i2s_pre", i2s_pre_p, 0,
724 MUX(0, "i2s0_clkout_s", i2s_clkout_p, 0,
730 MUX(0, "spdif_src", cpll_gpll_p, 0,
732 MUX(0, "spdif_mux", spdif_p, 0,
774 MUX(0, "uart_src", cpll_gpll_p, 0,
821 MUX(SCLK_MAC, "mac_clk", mac_p, 0,
825 MUX(0, "sclk_hsadc_out", hsadcout_p, 0,
829 MUX(0, "wifi_src", wifi_p, 0,
850 MUX(0, "vip_src_s", cpll_gpll_p, 0,
861 MUX(0, "sclk_edp_24m_s", edp_24m_p, 0,
[all …]
H A Drk_cru.h173 #define MUX(_id, _name, _pn, _f, _mo, _ms, _mw) \ macro
/f-stack/freebsd/mips/ingenic/
H A Djz4780_clock.c154 MUX(JZ_CPCCR, 30, 2, 0x7),
161 MUX(JZ_CPCCR, 28, 2, 0x7),
182 MUX(JZ_CPCCR, 26, 2, 0x7),
189 MUX(JZ_CPCCR, 24, 2, 0x7),
210 MUX(JZ_DDCDR, 30, 2, 0x6),
217 MUX(JZ_VPUCDR, 30, 2, 0xe),
224 MUX(JZ_I2SCDR, 30, 1, 0xc),
231 MUX(JZ_I2SCDR, 31, 1, 0xc),
238 MUX(JZ_LP0CDR, 30, 2, 0xe),
245 MUX(JZ_LP1CDR, 30, 2, 0xe),
[all …]
/f-stack/freebsd/arm/nvidia/tegra124/
H A Dtegra124_car.c67 #define MUX(_id, cname, plists, o, s, w) \ macro
229 MUX(0, "pllD2_src", mux_pll_srcs, PLLD2_BASE, 25, 2),
230 MUX(0, "pllDP_src", mux_pll_srcs, PLLDP_BASE, 25, 2),
231 MUX(0, "pllC4_src", mux_pll_srcs, PLLC4_BASE, 25, 2),
232 MUX(0, "pllE_src1", mux_plle_src1, PLLE_AUX, 2, 1),
233 MUX(0, "pllE_src", mux_plle_src, PLLE_AUX, 28, 1),
236 MUX(0, "dsia_mux", mux_plld_out0_plld2_out0, PLLD_BASE, 25, 1),
237 MUX(0, "dsib_mux", mux_plld_out0_plld2_out0, PLLD2_BASE, 25, 1),
240 MUX(TEGRA124_CLK_XUSB_HS_SRC, "xusb_hs", mux_xusb_hs, CLK_SOURCE_XUSB_SS, 25, 1),
241 MUX(0, "xusb_ss_mux", mux_xusb_ss, CLK_SOURCE_XUSB_SS, 24, 1),
/f-stack/freebsd/contrib/device-tree/Bindings/i2c/
H A Di2c-mux-gpmux.txt11 | .------. | .------+ child bus A, on MUX value set to 0
13 | '------' | '--+---+ child bus B, on MUX value set to 1
15 | | MUX- | | | | | |
/f-stack/freebsd/contrib/device-tree/Bindings/interrupt-controller/
H A Dbrcm,bcm7120-l2-intc.txt26 0 -----[ MUX ] ------------|==========> GIC interrupt 75
29 1 -----[ MUX ] --------)---|==========> GIC interrupt 76
32 2 -----[ MUX ] --------)---|==========> GIC interrupt 77
/f-stack/freebsd/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,gsbi.txt14 - qcom,mode : indicates MUX value for configuration of the serial interface.
18 - qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference
/f-stack/freebsd/contrib/device-tree/Bindings/display/exynos/
H A Dexynos_hdmi.txt46 i) tmds_clko_user: MUX used to switch between oscclk and tmds_clko,
49 k) pixel_clko_user: MUX used to switch between oscclk and pixel_clko,
/f-stack/freebsd/contrib/device-tree/Bindings/pinctrl/
H A Drockchip,pinctrl.txt73 setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
74 The MUX 0 means gpio and MUX 1 to N mean the specific device function.
/f-stack/freebsd/contrib/device-tree/Bindings/dma/
H A Dst,stm32-dmamux.yaml7 title: STMicroelectronics STM32 DMA MUX (DMA request router) bindings
H A Dlpc1850-dmamux.txt1 NXP LPC18xx/43xx DMA MUX (DMA request router)
/f-stack/freebsd/arm64/nvidia/tegra210/
H A Dtegra210_car.c68 #define MUX(_id, cname, plists, o, s, w) \ macro
240 MUX(TEGRA210_CLK_XUSB_HS_SRC, "xusb_hs", mux_xusb_hs, CLK_SOURCE_XUSB_SS, 25, 2),
241 MUX(0, "xusb_ssp", mux_xusb_ssp, CLK_SOURCE_XUSB_SS, 24, 1),
H A Dtegra210_clk_pll.c155 #define MUX(_id, cname, plists, o, s, w) \ macro
494 MUX(0, "pllD2_src", mux_pll_srcs, PLLD2_BASE, 25, 2),
495 MUX(0, "pllDP_src", mux_pll_srcs, PLLDP_BASE, 25, 2),
496 MUX(0, "pllC4_src", mux_pll_srcs, PLLC4_BASE, 25, 2),
497 MUX(0, "pllE_src1", mux_plle_src1, PLLE_AUX, 2, 1),
498 MUX(0, "pllE_src", mux_plle_src, PLLE_AUX, 28, 1),
/f-stack/freebsd/contrib/device-tree/Bindings/bus/
H A Dnvidia,tegra20-gmi.txt44 - nvidia,snor-mux-mode: Enable address/data MUX mode.
56 - nvidia,snor-muxed-width: Number of cycles MUX address/data asserted on the
/f-stack/freebsd/contrib/device-tree/Bindings/ata/
H A Dapm-xgene.txt18 controller MUX memory resource if required.
/f-stack/freebsd/contrib/device-tree/Bindings/soc/mediatek/
H A Dscpsys.txt38 Required clocks for MT6765: MUX: "mm", "mfg"
/f-stack/freebsd/contrib/device-tree/src/arm/
H A Daspeed-bmc-opp-witherspoon.dts345 /* MUX ->
523 /* MUX
H A Dr8a7740-armadillo800eva.dts267 /* DBGMD/LCDC0/FSIA MUX */
H A Daspeed-bmc-opp-swift.dts331 /* MUX ->
905 /* MUX
/f-stack/freebsd/contrib/device-tree/src/arm64/marvell/
H A Dcn9131-db.dts146 /* On-board MUX does not allow higher frequencies */
H A Dcn9130-db.dts319 /* On-board MUX does not allow higher frequencies */

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