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Searched refs:MLX5_WQE_DSEG_SIZE (Results 1 – 4 of 4) sorted by relevance

/f-stack/dpdk/drivers/net/mlx5/
H A Dmlx5_txq.c873 MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE); in txq_set_params()
874 temp -= MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE; in txq_set_params()
876 temp += MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE; in txq_set_params()
881 MLX5_WQE_DSEG_SIZE * 2); in txq_set_params()
903 MLX5_WQE_DSEG_SIZE * 2); in txq_set_params()
944 MLX5_WQE_DSEG_SIZE); in txq_set_params()
958 MLX5_WQE_DSEG_SIZE); in txq_set_params()
H A Dmlx5_ethdev.c270 MLX5_WQE_DSEG_SIZE * 2); in mlx5_set_txlimit_params()
275 MLX5_WQE_DSEG_SIZE - in mlx5_set_txlimit_params()
H A Dmlx5_rxtx.c4311 MLX5_WQE_DSEG_SIZE)); in mlx5_tx_burst_empw_inline()
4319 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE); in mlx5_tx_burst_empw_inline()
4320 MLX5_ASSERT((room % MLX5_WQE_DSEG_SIZE) == 0); in mlx5_tx_burst_empw_inline()
4413 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE); in mlx5_tx_burst_empw_inline()
4420 room -= MLX5_WQE_DSEG_SIZE; in mlx5_tx_burst_empw_inline()
4487 if (unlikely(!nlim || room < MLX5_WQE_DSEG_SIZE)) in mlx5_tx_burst_empw_inline()
4679 MLX5_WQE_DSEG_SIZE + in mlx5_tx_burst_single_send()
4682 MLX5_WQE_DSEG_SIZE + in mlx5_tx_burst_single_send()
5576 static_assert(MLX5_WQE_DSEG_SIZE == MLX5_WSEG_SIZE, in mlx5_select_tx_function()
/f-stack/dpdk/drivers/common/mlx5/
H A Dmlx5_prm.h42 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg) macro
81 MLX5_WQE_DSEG_SIZE + \
112 MLX5_WQE_DSEG_SIZE)
120 MLX5_WQE_DSEG_SIZE + \