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Searched refs:MLX5_DBR_SIZE (Results 1 – 3 of 3) sorted by relevance

/f-stack/dpdk/drivers/common/mlx5/
H A Dmlx5_common.c201 return (i * CHAR_BIT * sizeof(uint64_t) + j) * MLX5_DBR_SIZE; in mlx5_get_dbr()
239 offset /= MLX5_DBR_SIZE; in mlx5_release_dbr()
H A Dmlx5_common.h222 #define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE macro
225 #define MLX5_DBR_PAGE_SIZE (MLX5_DBR_PER_PAGE * MLX5_DBR_SIZE)
/f-stack/dpdk/drivers/net/mlx5/
H A Dmlx5_txpp.c254 umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); in mlx5_txpp_create_rearm_queue()
255 umem_size += MLX5_DBR_SIZE; in mlx5_txpp_create_rearm_queue()
303 umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); in mlx5_txpp_create_rearm_queue()
304 umem_size += MLX5_DBR_SIZE; in mlx5_txpp_create_rearm_queue()
492 umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); in mlx5_txpp_create_clock_queue()
493 umem_size += MLX5_DBR_SIZE; in mlx5_txpp_create_clock_queue()
547 umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); in mlx5_txpp_create_clock_queue()
548 umem_size += MLX5_DBR_SIZE; in mlx5_txpp_create_clock_queue()