Searched refs:MDIO_WC_REG_RX0_PCI_CTRL (Results 1 – 2 of 2) sorted by relevance
5725 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba macro
600 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba macro4716 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val); in elink_warpcore_enable_AN_KR()4731 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), in elink_warpcore_enable_AN_KR()