| /f-stack/freebsd/contrib/device-tree/Bindings/net/ |
| H A D | marvell-orion-mdio.txt | 1 * Marvell MDIO Ethernet Controller interface
5 identical unit that provides an interface with the MDIO bus.
12 - reg: address and length of the MDIO registers. When an interrupt is
19 - clocks: phandle for up to four required clocks for the MDIO instance
21 The child nodes of the MDIO driver are the individual PHY devices
22 connected to this MDIO bus. They must have a "reg" property given the
23 PHY address on the MDIO bus.
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| H A D | mdio.yaml | 7 title: MDIO Bus Generic Binding
15 These are generic properties that can apply to any MDIO bus. Any
16 MDIO bus must have a list of child nodes, one per device on the
34 lines of all devices on that MDIO bus.
38 RESET pulse width in microseconds. It applies to all MDIO devices
44 Delay after reset deassert in microseconds. It applies to all MDIO
51 Desired MDIO bus clock frequency in Hz. Values greater than IEEE 802.3
75 If set, indicates the MDIO device does not correctly release
77 MDIO transaction.
88 The GPIO phandle and specifier for the MDIO reset signal.
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| H A D | cavium-mdio.txt | 1 * System Management Interface (SMI) / MDIO
11 - reg: The base address of the MDIO bus controller register bank.
15 - #size-cells: Must be <0>. MDIO addresses have no size component.
17 Typically an MDIO bus might have several children.
33 * System Management Interface (SMI) / MDIO Nexus
48 - ranges: As needed for mapping of the MDIO bus device registers.
50 - assigned-addresses: As needed for mapping of the MDIO bus device registers.
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| H A D | brcm,unimac-mdio.txt | 1 * Broadcom UniMAC MDIO bus controller
9 larger than 16-bits MDIO transactions
16 Ethernet switch this MDIO block is integrated from, or must be two, if there
22 - clocks: A reference to the clock supplying the MDIO bus controller
23 - clock-frequency: the MDIO bus clock that must be output by the MDIO bus
26 Child nodes of this MDIO bus controller node are standard Ethernet PHY device
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| H A D | hisilicon-hns-mdio.txt | 1 Hisilicon MDIO bus controller
10 - reg: The base address of the MDIO bus controller register bank.
12 - #size-cells: Must be <0>. MDIO addresses have no size component.
14 Typically an MDIO bus might have several children.
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| H A D | mscc-miim.txt | 1 Microsemi MII Management Controller (MIIM) / MDIO
6 - reg: The base address of the MDIO bus controller register bank. Optionally, a
10 - #size-cells: Must be <0>. MDIO addresses have no size component.
13 Typically an MDIO bus might have several children.
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| H A D | brcm,mdio-mux-iproc.txt | 1 Properties for an MDIO bus multiplexer found in Broadcom iProc based SoCs.
3 This MDIO bus multiplexer defines buses that could be internal as well as
4 external to SoCs and could accept MDIO transaction compatible to C-22 or
6 properties as well to generate desired MDIO transaction on appropriate bus.
10 MDIO multiplexer node:
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| H A D | aspeed,ast2600-mdio.yaml | 7 title: ASPEED AST2600 MDIO Controller
13 The ASPEED AST2600 MDIO controller is the third iteration of ASPEED's MDIO
25 description: The register range of the MDIO controller instance
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| H A D | mdio-gpio.txt | 1 MDIO on GPIOs
6 MDC and MDIO lines connected to GPIO controllers are listed in the
9 MDC, MDIO.
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| H A D | mdio-mux-multiplexer.txt | 1 Properties for an MDIO bus multiplexer consumer device
3 This is a special case of MDIO mux when MDIO mux is defined as a consumer
7 Required properties in addition to the MDIO Bus multiplexer properties:
11 - mdio-parent-bus : phandle to the parent MDIO bus.
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| H A D | brcm,iproc-mdio.txt | 1 * Broadcom iProc MDIO bus controller
5 - reg: address and length of the register set for the MDIO interface
9 Child nodes of this MDIO bus controller node are standard Ethernet PHY device
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| H A D | mdio-mux.txt | 1 Common MDIO bus multiplexer/switch properties.
3 An MDIO bus multiplexer/switch will have several child busses that are
4 numbered uniquely in a device dependent manner. The nodes for an MDIO
12 - mdio-parent-bus : phandle to the parent MDIO bus.
24 /* The parent MDIO bus. */
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| H A D | apm-xgene-mdio.txt | 1 APM X-Gene SoC MDIO node
3 MDIO node is defined to describe on-chip MDIO controller.
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| H A D | ti,davinci-mdio.yaml | 7 title: TI SoC Davinci/Keystone2 MDIO Controller
13 TI SoC Davinci/Keystone2 MDIO Controller
38 description: MDIO Bus frequency
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| H A D | fsl-fman.txt | 10 - FMan MDIO Node
369 FMan MDIO Node
373 The MDIO is a bus to which the PHY devices are connected.
401 Usage: required for external MDIO
403 Definition: Event interrupt of external MDIO controller.
406 Usage: required for internal MDIO
411 MDIO are different. Must be included for internal MDIO.
418 set when reading internal PCS registers. MDIO reads to
435 Example for FMan v2 external MDIO:
443 Example for FMan v2 internal MDIO:
[all …]
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| H A D | mdio-mux-meson-g12a.txt | 1 Properties for the MDIO bus multiplexer/glue of Amlogic G12a SoC family.
3 This is a special case of a MDIO bus multiplexer. It allows to choose between
5 MDIO bus.
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| H A D | mdio-mux-mmioreg.txt | 1 Properties for an MDIO bus multiplexer controlled by a memory-mapped device
3 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
24 For the "EMI2" MDIO bus, register 9 (BRDCFG1) controls the mux on that bus.
68 /* The parent MDIO bus. */
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| H A D | nixge.txt | 11 "ctrl": MDIO and PHY control and status region
19 - mdio subnode to indicate presence of MDIO controller
49 Examples (10G generic PHY, no MDIO):
65 Examples (1G generic fixed-link + MDIO):
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| H A D | fsl-enetc.txt | 14 1. The ENETC external port is connected to a MDIO configurable phy
16 1.1. Using the local ENETC Port MDIO interface
26 - phy-handle : Phandle to a PHY on the MDIO bus.
52 1.2. Using the central MDIO PCIe endpoint device
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| H A D | qca,ar71xx.yaml | 38 description: number of address cells for the MDIO bus
42 description: number of size cells on the MDIO bus
48 - description: MDIO clock
58 - description: MDIO reset
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| /f-stack/freebsd/contrib/device-tree/src/powerpc/ |
| H A D | kmeter1.dts | 148 0 1 3 0 2 0 /* MDIO */
174 0 1 3 0 2 0 /* MDIO */
200 0 1 3 0 2 0 /* MDIO */
220 0 1 3 0 2 0 /* MDIO */
238 0 1 3 0 2 0 /* MDIO */
256 0 1 3 0 2 0 /* MDIO */
274 0 1 3 0 2 0 /* MDIO */
362 /* Eth-1 (UCC5, MDIO 0x08, RMII) */
378 /* Eth-2 (UCC6, MDIO 0x09, RMII) */
394 /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
[all …]
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| /f-stack/freebsd/contrib/device-tree/Bindings/phy/ |
| H A D | brcm,mdio-mux-bus-pci.txt | 4 - reg: MDIO Bus number for the MDIO interface
10 - reg: MDIO Phy ID for the MDIO interface
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| /f-stack/freebsd/contrib/device-tree/Bindings/net/dsa/ |
| H A D | realtek-smi.txt | 5 bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
6 not use the MDIO protocol. This binding defines how to specify the
23 - mdio-gpios: GPIO line for the MDIO data line.
50 This defines the internal MDIO bus of the SMI device, mostly for the
58 See net/mdio.txt for additional MDIO bus properties.
67 /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
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| H A D | marvell.txt | 10 Marvell Switches are MDIO devices. The following properties should be
17 which is at a different MDIO base address in different switch families.
44 - mdio : Container of PHY and devices on the switches MDIO
46 - mdio? : Container of PHYs and devices on the external MDIO
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| /f-stack/freebsd/mips/conf/ |
| H A D | AP91.hints | 3 # arge0 MDIO bus
9 # arge1 MDIO bus doesn't exist on the AR7240
12 # MDIO bus.
21 hint.arge.0.mdio=mdioproxy1 # Hanging off the arswitch MDIO bus
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