| /f-stack/freebsd/arm64/freescale/imx/clk/ |
| H A D | imx_clk_gate.c | 46 #define MD4(_clk, off, clr, set ) \ macro
88 rv = MD4(clk, sc->offset, sc->mask << sc->shift, in imx_clk_gate_set_gate()
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| H A D | imx_clk_mux.c | 50 #define MD4(_clk, off, clr, set ) \ macro
106 rv = MD4(clk, sc->offset, sc->mask << sc->shift, in imx_clk_mux_set_mux()
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| /f-stack/freebsd/arm64/rockchip/clk/ |
| H A D | rk_clk_gate.c | 46 #define MD4(_clk, off, clr, set ) \ macro
103 rv = MD4(clk, sc->offset, sc->mask << sc->shift, in rk_clk_gate_set_gate()
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| H A D | rk_clk_mux.c | 51 #define MD4(_clk, off, clr, set ) \ macro
117 rv = MD4(clk, sc->offset, sc->mask << sc->shift, in rk_clk_mux_set_mux()
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| H A D | rk_clk_fract.c | 45 #define MD4(_clk, off, clr, set ) \ macro
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| /f-stack/freebsd/arm/nvidia/tegra124/ |
| H A D | tegra124_car.h | 36 #define MD4(sc, reg, mask, set) CLKDEV_MODIFY_4((sc)->clkdev, reg, mask, set) macro
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| H A D | tegra124_clk_per.c | 557 MD4(sc, sc->base_reg, PERLCK_ENA_MASK, PERLCK_ENA_MASK); in periph_init()
664 MD4(sc, sc->base_reg, sc->div_mask, in periph_set_freq()
766 MD4(sc, base_reg, mask, enable ? mask : 0); in pgate_set_gate()
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| H A D | tegra124_clk_pll.c | 721 MD4(sc, sc->iddq_reg, sc->iddq_mask, 0); in pll_set_std()
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| /f-stack/freebsd/arm64/nvidia/tegra210/ |
| H A D | tegra210_clk_per.c | 670 MD4(sc, sc->base_reg, PERLCK_ENA_MASK, PERLCK_ENA_MASK); in periph_init()
778 MD4(sc, sc->base_reg, sc->div_mask, in periph_set_freq()
880 MD4(sc, base_reg, mask, enable ? mask : 0); in pgate_set_gate()
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| H A D | tegra210_car.h | 37 #define MD4(sc, reg, mask, set) CLKDEV_MODIFY_4((sc)->clkdev, reg, mask, set) macro
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| H A D | tegra210_clk_pll.c | 919 MD4(sc, sc->iddq_reg, sc->iddq_mask, 0); in pll_set_std()
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