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Searched refs:JZ_SSICDR (Results 1 – 2 of 2) sorted by relevance

/f-stack/freebsd/mips/ingenic/
H A Djz4780_clock.c287 MUX(JZ_SSICDR, 30, 1, 0xc),
288 DIV(JZ_SSICDR, 0, 0, 8, 29, 28, 27),
294 MUX(JZ_SSICDR, 31, 1, 0xc),
H A Djz4780_regs.h239 #define JZ_SSICDR 0x00000074 /* SSI clock divider register */ macro