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Searched refs:JZ_SRBC (Results 1 – 2 of 2) sorted by relevance

/f-stack/freebsd/mips/ingenic/
H A Djz4780_clock.c751 reg = CSR_READ_4(sc, JZ_SRBC); in jz4780_ehci_enable()
753 CSR_WRITE_4(sc, JZ_SRBC, reg); in jz4780_ehci_enable()
757 reg = CSR_READ_4(sc, JZ_SRBC); in jz4780_ehci_enable()
759 CSR_WRITE_4(sc, JZ_SRBC, reg); in jz4780_ehci_enable()
H A Djz4780_regs.h339 #define JZ_SRBC 0x000000c4 /* Soft Reset & Bus Control */ macro