1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #ifndef _IXGBE_DCB_82599_H_ 6 #define _IXGBE_DCB_82599_H_ 7 8 /* DCB register definitions */ 9 #define IXGBE_RTTDCS_TDPAC 0x00000001 /* 0 Round Robin, 10 * 1 WSP - Weighted Strict Priority 11 */ 12 #define IXGBE_RTTDCS_VMPAC 0x00000002 /* 0 Round Robin, 13 * 1 WRR - Weighted Round Robin 14 */ 15 #define IXGBE_RTTDCS_TDRM 0x00000010 /* Transmit Recycle Mode */ 16 #define IXGBE_RTTDCS_BDPM 0x00400000 /* Bypass Data Pipe - must clear! */ 17 #define IXGBE_RTTDCS_BPBFSM 0x00800000 /* Bypass PB Free Space - must 18 * clear! 19 */ 20 #define IXGBE_RTTDCS_SPEED_CHG 0x80000000 /* Link speed change */ 21 22 /* Receive UP2TC mapping */ 23 #define IXGBE_RTRUP2TC_UP_SHIFT 3 24 #define IXGBE_RTRUP2TC_UP_MASK 7 25 /* Transmit UP2TC mapping */ 26 #define IXGBE_RTTUP2TC_UP_SHIFT 3 27 28 #define IXGBE_RTRPT4C_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */ 29 #define IXGBE_RTRPT4C_BWG_SHIFT 9 /* Offset to BWG index */ 30 #define IXGBE_RTRPT4C_GSP 0x40000000 /* GSP enable bit */ 31 #define IXGBE_RTRPT4C_LSP 0x80000000 /* LSP enable bit */ 32 33 #define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet 34 * buffers enable 35 */ 36 #define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores 37 * (RSS) enable 38 */ 39 40 /* RTRPCS Bit Masks */ 41 #define IXGBE_RTRPCS_RRM 0x00000002 /* Receive Recycle Mode enable */ 42 /* Receive Arbitration Control: 0 Round Robin, 1 DFP */ 43 #define IXGBE_RTRPCS_RAC 0x00000004 44 #define IXGBE_RTRPCS_ARBDIS 0x00000040 /* Arbitration disable bit */ 45 46 /* RTTDT2C Bit Masks */ 47 #define IXGBE_RTTDT2C_MCL_SHIFT 12 48 #define IXGBE_RTTDT2C_BWG_SHIFT 9 49 #define IXGBE_RTTDT2C_GSP 0x40000000 50 #define IXGBE_RTTDT2C_LSP 0x80000000 51 52 #define IXGBE_RTTPT2C_MCL_SHIFT 12 53 #define IXGBE_RTTPT2C_BWG_SHIFT 9 54 #define IXGBE_RTTPT2C_GSP 0x40000000 55 #define IXGBE_RTTPT2C_LSP 0x80000000 56 57 /* RTTPCS Bit Masks */ 58 #define IXGBE_RTTPCS_TPPAC 0x00000020 /* 0 Round Robin, 59 * 1 SP - Strict Priority 60 */ 61 #define IXGBE_RTTPCS_ARBDIS 0x00000040 /* Arbiter disable */ 62 #define IXGBE_RTTPCS_TPRM 0x00000100 /* Transmit Recycle Mode enable */ 63 #define IXGBE_RTTPCS_ARBD_SHIFT 22 64 #define IXGBE_RTTPCS_ARBD_DCB 0x4 /* Arbitration delay in DCB mode */ 65 66 #define IXGBE_TXPBTHRESH_DCB 0xA /* THRESH value for DCB mode */ 67 68 /* SECTXMINIFG DCB */ 69 #define IXGBE_SECTX_DCB 0x00001F00 /* DCB TX Buffer SEC IFG */ 70 71 /* BCN register definitions */ 72 #define IXGBE_RTTBCNRC_RF_INT_SHIFT 14 73 #define IXGBE_RTTBCNRC_RS_ENA 0x80000000 74 75 #define IXGBE_RTTBCNCR_MNG_CMTGI 0x00000001 76 #define IXGBE_RTTBCNCR_MGN_BCNA_MODE 0x00000002 77 #define IXGBE_RTTBCNCR_RSV7_11_SHIFT 5 78 #define IXGBE_RTTBCNCR_G 0x00000400 79 #define IXGBE_RTTBCNCR_I 0x00000800 80 #define IXGBE_RTTBCNCR_H 0x00001000 81 #define IXGBE_RTTBCNCR_VER_SHIFT 14 82 #define IXGBE_RTTBCNCR_CMT_ETH_SHIFT 16 83 84 #define IXGBE_RTTBCNACL_SMAC_L_SHIFT 16 85 86 #define IXGBE_RTTBCNTG_BCNA_MODE 0x80000000 87 88 #define IXGBE_RTTBCNRTT_TS_SHIFT 3 89 #define IXGBE_RTTBCNRTT_TXQ_IDX_SHIFT 16 90 91 #define IXGBE_RTTBCNRD_BCN_CLEAR_ALL 0x00000002 92 #define IXGBE_RTTBCNRD_DRIFT_FAC_SHIFT 2 93 #define IXGBE_RTTBCNRD_DRIFT_INT_SHIFT 16 94 #define IXGBE_RTTBCNRD_DRIFT_ENA 0x80000000 95 96 97 /* DCB driver APIs */ 98 99 /* DCB PFC */ 100 s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *, u8, u8 *); 101 102 /* DCB stats */ 103 s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *, 104 struct ixgbe_dcb_config *); 105 s32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *, 106 struct ixgbe_hw_stats *, u8); 107 s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *, 108 struct ixgbe_hw_stats *, u8); 109 110 /* DCB config arbiters */ 111 s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, 112 u8 *, u8 *); 113 s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, 114 u8 *, u8 *, u8 *); 115 s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, u8 *, 116 u8 *, u8 *); 117 118 /* DCB initialization */ 119 s32 ixgbe_dcb_config_82599(struct ixgbe_hw *, 120 struct ixgbe_dcb_config *); 121 122 s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *, int, u16 *, u16 *, u8 *, 123 u8 *, u8 *); 124 #endif /* _IXGBE_DCB_82959_H_ */ 125