1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #ifndef _IGC_82575_H_ 6 #define _IGC_82575_H_ 7 8 #define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \ 9 (ID_LED_DEF1_DEF2 << 8) | \ 10 (ID_LED_DEF1_DEF2 << 4) | \ 11 (ID_LED_OFF1_ON2)) 12 /* 13 * Receive Address Register Count 14 * Number of high/low register pairs in the RAR. The RAR (Receive Address 15 * Registers) holds the directed and multicast addresses that we monitor. 16 * These entries are also used for MAC-based filtering. 17 */ 18 /* 19 * For 82576, there are an additional set of RARs that begin at an offset 20 * separate from the first set of RARs. 21 */ 22 #define IGC_RAR_ENTRIES_82575 16 23 #define IGC_RAR_ENTRIES_82576 24 24 #define IGC_RAR_ENTRIES_82580 24 25 #define IGC_RAR_ENTRIES_I350 32 26 #define IGC_SW_SYNCH_MB 0x00000100 27 #define IGC_STAT_DEV_RST_SET 0x00100000 28 29 struct igc_adv_data_desc { 30 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 31 union { 32 u32 data; 33 struct { 34 u32 datalen:16; /* Data buffer length */ 35 u32 rsvd:4; 36 u32 dtyp:4; /* Descriptor type */ 37 u32 dcmd:8; /* Descriptor command */ 38 } config; 39 } lower; 40 union { 41 u32 data; 42 struct { 43 u32 status:4; /* Descriptor status */ 44 u32 idx:4; 45 u32 popts:6; /* Packet Options */ 46 u32 paylen:18; /* Payload length */ 47 } options; 48 } upper; 49 }; 50 51 #define IGC_TXD_DTYP_ADV_C 0x2 /* Advanced Context Descriptor */ 52 #define IGC_TXD_DTYP_ADV_D 0x3 /* Advanced Data Descriptor */ 53 #define IGC_ADV_TXD_CMD_DEXT 0x20 /* Descriptor extension (0 = legacy) */ 54 #define IGC_ADV_TUCMD_IPV4 0x2 /* IP Packet Type: 1=IPv4 */ 55 #define IGC_ADV_TUCMD_IPV6 0x0 /* IP Packet Type: 0=IPv6 */ 56 #define IGC_ADV_TUCMD_L4T_UDP 0x0 /* L4 Packet TYPE of UDP */ 57 #define IGC_ADV_TUCMD_L4T_TCP 0x4 /* L4 Packet TYPE of TCP */ 58 #define IGC_ADV_TUCMD_MKRREQ 0x10 /* Indicates markers are required */ 59 #define IGC_ADV_DCMD_EOP 0x1 /* End of Packet */ 60 #define IGC_ADV_DCMD_IFCS 0x2 /* Insert FCS (Ethernet CRC) */ 61 #define IGC_ADV_DCMD_RS 0x8 /* Report Status */ 62 #define IGC_ADV_DCMD_VLE 0x40 /* Add VLAN tag */ 63 #define IGC_ADV_DCMD_TSE 0x80 /* TCP Seg enable */ 64 /* Extended Device Control */ 65 #define IGC_CTRL_EXT_NSICR 0x00000001 /* Disable Intr Clear all on read */ 66 67 struct igc_adv_context_desc { 68 union { 69 u32 ip_config; 70 struct { 71 u32 iplen:9; 72 u32 maclen:7; 73 u32 vlan_tag:16; 74 } fields; 75 } ip_setup; 76 u32 seq_num; 77 union { 78 u64 l4_config; 79 struct { 80 u32 mkrloc:9; 81 u32 tucmd:11; 82 u32 dtyp:4; 83 u32 adv:8; 84 u32 rsvd:4; 85 u32 idx:4; 86 u32 l4len:8; 87 u32 mss:16; 88 } fields; 89 } l4_setup; 90 }; 91 92 /* SRRCTL bit definitions */ 93 #define IGC_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 94 #define IGC_SRRCTL_DESCTYPE_LEGACY 0x00000000 95 #define IGC_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 96 #define IGC_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 97 #define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000 98 #define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 99 #define IGC_SRRCTL_DESCTYPE_MASK 0x0E000000 100 #define IGC_SRRCTL_TIMESTAMP 0x40000000 101 #define IGC_SRRCTL_DROP_EN 0x80000000 102 103 #define IGC_SRRCTL_BSIZEPKT_MASK 0x0000007F 104 #define IGC_SRRCTL_BSIZEHDR_MASK 0x00003F00 105 106 #define IGC_TX_HEAD_WB_ENABLE 0x1 107 #define IGC_TX_SEQNUM_WB_ENABLE 0x2 108 109 #define IGC_MRQC_ENABLE_RSS_4Q 0x00000002 110 #define IGC_MRQC_ENABLE_VMDQ 0x00000003 111 #define IGC_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005 112 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 113 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 114 #define IGC_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000 115 #define IGC_MRQC_ENABLE_RSS_8Q 0x00000002 116 117 #define IGC_VMRCTL_MIRROR_PORT_SHIFT 8 118 #define IGC_VMRCTL_MIRROR_DSTPORT_MASK (7 << \ 119 IGC_VMRCTL_MIRROR_PORT_SHIFT) 120 #define IGC_VMRCTL_POOL_MIRROR_ENABLE (1 << 0) 121 #define IGC_VMRCTL_UPLINK_MIRROR_ENABLE (1 << 1) 122 #define IGC_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2) 123 124 #define IGC_EICR_TX_QUEUE ( \ 125 IGC_EICR_TX_QUEUE0 | \ 126 IGC_EICR_TX_QUEUE1 | \ 127 IGC_EICR_TX_QUEUE2 | \ 128 IGC_EICR_TX_QUEUE3) 129 130 #define IGC_EICR_RX_QUEUE ( \ 131 IGC_EICR_RX_QUEUE0 | \ 132 IGC_EICR_RX_QUEUE1 | \ 133 IGC_EICR_RX_QUEUE2 | \ 134 IGC_EICR_RX_QUEUE3) 135 136 #define IGC_EIMS_RX_QUEUE IGC_EICR_RX_QUEUE 137 #define IGC_EIMS_TX_QUEUE IGC_EICR_TX_QUEUE 138 139 #define EIMS_ENABLE_MASK ( \ 140 IGC_EIMS_RX_QUEUE | \ 141 IGC_EIMS_TX_QUEUE | \ 142 IGC_EIMS_TCP_TIMER | \ 143 IGC_EIMS_OTHER) 144 145 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 146 #define IGC_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ 147 #define IGC_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ 148 #define IGC_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ 149 #define IGC_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ 150 #define IGC_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ 151 #define IGC_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ 152 #define IGC_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ 153 #define IGC_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ 154 155 #define IGC_RXDADV_RSSTYPE_MASK 0x0000000F 156 #define IGC_RXDADV_RSSTYPE_SHIFT 12 157 #define IGC_RXDADV_HDRBUFLEN_MASK 0x7FE0 158 #define IGC_RXDADV_HDRBUFLEN_SHIFT 5 159 #define IGC_RXDADV_SPLITHEADER_EN 0x00001000 160 #define IGC_RXDADV_SPH 0x8000 161 #define IGC_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */ 162 #define IGC_RXDADV_ERR_HBO 0x00800000 163 164 /* RSS Hash results */ 165 #define IGC_RXDADV_RSSTYPE_NONE 0x00000000 166 #define IGC_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 167 #define IGC_RXDADV_RSSTYPE_IPV4 0x00000002 168 #define IGC_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 169 #define IGC_RXDADV_RSSTYPE_IPV6_EX 0x00000004 170 #define IGC_RXDADV_RSSTYPE_IPV6 0x00000005 171 #define IGC_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 172 #define IGC_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 173 #define IGC_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 174 #define IGC_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 175 176 /* RSS Packet Types as indicated in the receive descriptor */ 177 #define IGC_RXDADV_PKTTYPE_ILMASK 0x000000F0 178 #define IGC_RXDADV_PKTTYPE_TLMASK 0x00000F00 179 #define IGC_RXDADV_PKTTYPE_NONE 0x00000000 180 #define IGC_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */ 181 #define IGC_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPV4 hdr + extensions */ 182 #define IGC_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPV6 hdr present */ 183 #define IGC_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPV6 hdr + extensions */ 184 #define IGC_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 185 #define IGC_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 186 #define IGC_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 187 #define IGC_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 188 189 #define IGC_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 190 #define IGC_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 191 #define IGC_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ 192 #define IGC_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ 193 #define IGC_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ 194 #define IGC_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ 195 196 /* LinkSec results */ 197 /* Security Processing bit Indication */ 198 #define IGC_RXDADV_LNKSEC_STATUS_SECP 0x00020000 199 #define IGC_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000 200 #define IGC_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000 201 #define IGC_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000 202 #define IGC_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000 203 204 #define IGC_RXDADV_IPSEC_STATUS_SECP 0x00020000 205 #define IGC_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000 206 #define IGC_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000 207 #define IGC_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000 208 #define IGC_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED 0x18000000 209 210 #define IGC_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wbk flushing */ 211 /* Tx Queue Arbitration Priority 0=low, 1=high */ 212 #define IGC_TXDCTL_PRIORITY 0x08000000 213 214 #define IGC_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. wbk flushing */ 215 216 /* Direct Cache Access (DCA) definitions */ 217 #define IGC_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 218 #define IGC_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 219 220 #define IGC_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ 221 #define IGC_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 222 223 #define IGC_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 224 #define IGC_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ 225 #define IGC_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header ena */ 226 #define IGC_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload ena */ 227 #define IGC_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx Desc Relax Order */ 228 229 #define IGC_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 230 #define IGC_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 231 #define IGC_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */ 232 #define IGC_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ 233 #define IGC_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */ 234 235 #define IGC_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */ 236 #define IGC_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */ 237 #define IGC_DCA_TXCTRL_CPUID_SHIFT_82576 24 /* Tx CPUID */ 238 #define IGC_DCA_RXCTRL_CPUID_SHIFT_82576 24 /* Rx CPUID */ 239 240 /* Additional interrupt register bit definitions */ 241 #define IGC_ICR_LSECPNS 0x00000020 /* PN threshold - server */ 242 #define IGC_IMS_LSECPNS IGC_ICR_LSECPNS /* PN threshold - server */ 243 #define IGC_ICS_LSECPNS IGC_ICR_LSECPNS /* PN threshold - server */ 244 245 /* ETQF register bit definitions */ 246 #define IGC_ETQF_FILTER_ENABLE (1 << 26) 247 #define IGC_ETQF_IMM_INT (1 << 29) 248 #define IGC_ETQF_QUEUE_ENABLE (1 << 31) 249 /* 250 * ETQF filter list: one static filter per filter consumer. This is 251 * to avoid filter collisions later. Add new filters 252 * here!! 253 * 254 * Current filters: 255 * EAPOL 802.1x (0x888e): Filter 0 256 */ 257 #define IGC_ETQF_FILTER_EAPOL 0 258 259 #define IGC_FTQF_MASK_SOURCE_ADDR_BP 0x20000000 260 #define IGC_FTQF_MASK_DEST_ADDR_BP 0x40000000 261 #define IGC_FTQF_MASK_SOURCE_PORT_BP 0x80000000 262 263 #define IGC_NVM_APME_82575 0x0400 264 #define MAX_NUM_VFS 7 265 266 #define IGC_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof cntrl */ 267 #define IGC_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof cntrl */ 268 #define IGC_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */ 269 #define IGC_DTXSWC_VLAN_SPOOF_SHIFT 8 270 #define IGC_DTXSWC_LLE_SHIFT 16 271 #define IGC_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */ 272 273 /* Easy defines for setting default pool, would normally be left a zero */ 274 #define IGC_VT_CTL_DEFAULT_POOL_SHIFT 7 275 #define IGC_VT_CTL_DEFAULT_POOL_MASK (0x7 << IGC_VT_CTL_DEFAULT_POOL_SHIFT) 276 277 /* Other useful VMD_CTL register defines */ 278 #define IGC_VT_CTL_IGNORE_MAC (1 << 28) 279 #define IGC_VT_CTL_DISABLE_DEF_POOL (1 << 29) 280 #define IGC_VT_CTL_VM_REPL_EN (1 << 30) 281 282 /* Per VM Offload register setup */ 283 #define IGC_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */ 284 #define IGC_VMOLR_LPE 0x00010000 /* Accept Long packet */ 285 #define IGC_VMOLR_RSSE 0x00020000 /* Enable RSS */ 286 #define IGC_VMOLR_AUPE 0x01000000 /* Accept untagged packets */ 287 #define IGC_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */ 288 #define IGC_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */ 289 #define IGC_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */ 290 #define IGC_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */ 291 #define IGC_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */ 292 #define IGC_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */ 293 294 #define IGC_VMOLR_VPE 0x00800000 /* VLAN promiscuous enable */ 295 #define IGC_VMOLR_UPE 0x20000000 /* Unicast promisuous enable */ 296 #define IGC_DVMOLR_HIDVLAN 0x20000000 /* Vlan hiding enable */ 297 #define IGC_DVMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */ 298 #define IGC_DVMOLR_STRCRC 0x80000000 /* CRC stripping enable */ 299 300 #define IGC_PBRWAC_WALPB 0x00000007 /* Wrap around event on LAN Rx PB */ 301 #define IGC_PBRWAC_PBE 0x00000008 /* Rx packet buffer empty */ 302 303 #define IGC_VLVF_ARRAY_SIZE 32 304 #define IGC_VLVF_VLANID_MASK 0x00000FFF 305 #define IGC_VLVF_POOLSEL_SHIFT 12 306 #define IGC_VLVF_POOLSEL_MASK (0xFF << IGC_VLVF_POOLSEL_SHIFT) 307 #define IGC_VLVF_LVLAN 0x00100000 308 #define IGC_VLVF_VLANID_ENABLE 0x80000000 309 310 #define IGC_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */ 311 #define IGC_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */ 312 313 #define IGC_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 314 315 #define IGC_IOVCTL 0x05BBC 316 #define IGC_IOVCTL_REUSE_VFQ 0x00000001 317 318 #define IGC_RPLOLR_STRVLAN 0x40000000 319 #define IGC_RPLOLR_STRCRC 0x80000000 320 321 #define IGC_TCTL_EXT_COLD 0x000FFC00 322 #define IGC_TCTL_EXT_COLD_SHIFT 10 323 324 #define IGC_DTXCTL_8023LL 0x0004 325 #define IGC_DTXCTL_VLAN_ADDED 0x0008 326 #define IGC_DTXCTL_OOS_ENABLE 0x0010 327 #define IGC_DTXCTL_MDP_EN 0x0020 328 #define IGC_DTXCTL_SPOOF_INT 0x0040 329 330 #define IGC_EEPROM_PCS_AUTONEG_DISABLE_BIT (1 << 14) 331 332 #define ALL_QUEUES 0xFFFF 333 334 s32 igc_reset_init_script_82575(struct igc_hw *hw); 335 s32 igc_init_nvm_params_82575(struct igc_hw *hw); 336 337 /* Rx packet buffer size defines */ 338 #define IGC_RXPBS_SIZE_MASK_82576 0x0000007F 339 void igc_vmdq_set_loopback_pf(struct igc_hw *hw, bool enable); 340 void igc_vmdq_set_anti_spoofing_pf(struct igc_hw *hw, bool enable, int pf); 341 void igc_vmdq_set_replication_pf(struct igc_hw *hw, bool enable); 342 343 enum igc_promisc_type { 344 igc_promisc_disabled = 0, /* all promisc modes disabled */ 345 igc_promisc_unicast = 1, /* unicast promiscuous enabled */ 346 igc_promisc_multicast = 2, /* multicast promiscuous enabled */ 347 igc_promisc_enabled = 3, /* both uni and multicast promisc */ 348 igc_num_promisc_types 349 }; 350 351 #endif /* _IGC_82575_H_ */ 352