1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #ifndef _IGC_ICH8LAN_H_ 6 #define _IGC_ICH8LAN_H_ 7 8 #define ICH_FLASH_GFPREG 0x0000 9 #define ICH_FLASH_HSFSTS 0x0004 10 #define ICH_FLASH_HSFCTL 0x0006 11 #define ICH_FLASH_FADDR 0x0008 12 #define ICH_FLASH_FDATA0 0x0010 13 14 /* Requires up to 10 seconds when MNG might be accessing part. */ 15 #define ICH_FLASH_READ_COMMAND_TIMEOUT 10000000 16 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000 17 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000 18 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF 19 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 20 21 #define ICH_CYCLE_READ 0 22 #define ICH_CYCLE_WRITE 2 23 #define ICH_CYCLE_ERASE 3 24 25 #define FLASH_GFPREG_BASE_MASK 0x1FFF 26 #define FLASH_SECTOR_ADDR_SHIFT 12 27 28 #define ICH_FLASH_SEG_SIZE_256 256 29 #define ICH_FLASH_SEG_SIZE_4K 4096 30 #define ICH_FLASH_SEG_SIZE_8K 8192 31 #define ICH_FLASH_SEG_SIZE_64K 65536 32 33 #define IGC_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ 34 /* FW established a valid mode */ 35 #define IGC_ICH_FWSM_FW_VALID 0x00008000 36 #define IGC_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */ 37 #define IGC_ICH_FWSM_PCIM2PCI_COUNT 2000 38 39 #define IGC_ICH_MNG_IAMT_MODE 0x2 40 41 #define IGC_FWSM_WLOCK_MAC_MASK 0x0380 42 #define IGC_FWSM_WLOCK_MAC_SHIFT 7 43 #define IGC_FWSM_ULP_CFG_DONE 0x00000400 /* Low power cfg done */ 44 45 /* Shared Receive Address Registers */ 46 #define IGC_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8)) 47 #define IGC_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8)) 48 49 #define IGC_H2ME 0x05B50 /* Host to ME */ 50 #define IGC_H2ME_ULP 0x00000800 /* ULP Indication Bit */ 51 #define IGC_H2ME_ENFORCE_SETTINGS 0x00001000 /* Enforce Settings */ 52 53 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ 54 (ID_LED_OFF1_OFF2 << 8) | \ 55 (ID_LED_OFF1_ON2 << 4) | \ 56 (ID_LED_DEF1_DEF2)) 57 58 #define IGC_ICH_NVM_SIG_WORD 0x13 59 #define IGC_ICH_NVM_SIG_MASK 0xC000 60 #define IGC_ICH_NVM_VALID_SIG_MASK 0xC0 61 #define IGC_ICH_NVM_SIG_VALUE 0x80 62 63 #define IGC_ICH8_LAN_INIT_TIMEOUT 1500 64 65 /* FEXT register bit definition */ 66 #define IGC_FEXT_PHY_CABLE_DISCONNECTED 0x00000004 67 68 #define IGC_FEXTNVM_SW_CONFIG 1 69 #define IGC_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* different on ICH8M */ 70 71 #define IGC_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000 72 #define IGC_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000 73 74 #define IGC_FEXTNVM4_BEACON_DURATION_MASK 0x7 75 #define IGC_FEXTNVM4_BEACON_DURATION_8USEC 0x7 76 #define IGC_FEXTNVM4_BEACON_DURATION_16USEC 0x3 77 78 #define IGC_FEXTNVM6_REQ_PLL_CLK 0x00000100 79 #define IGC_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200 80 #define IGC_FEXTNVM6_K1_OFF_ENABLE 0x80000000 81 /* bit for disabling packet buffer read */ 82 #define IGC_FEXTNVM7_DISABLE_PB_READ 0x00040000 83 #define IGC_FEXTNVM7_SIDE_CLK_UNGATE 0x00000004 84 #define IGC_FEXTNVM7_DISABLE_SMB_PERST 0x00000020 85 #define IGC_FEXTNVM9_IOSFSB_CLKGATE_DIS 0x00000800 86 #define IGC_FEXTNVM9_IOSFSB_CLKREQ_DIS 0x00001000 87 #define IGC_FEXTNVM11_DISABLE_PB_READ 0x00000200 88 #define IGC_FEXTNVM11_DISABLE_MULR_FIX 0x00002000 89 90 /* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */ 91 #define IGC_RXDCTL_THRESH_UNIT_DESC 0x01000000 92 93 #define NVM_SIZE_MULTIPLIER 4096 /*multiplier for NVMS field*/ 94 #define IGC_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs*/ 95 #define IGC_CTRL_EXT_NVMVS 0x3 /*NVM valid sector */ 96 #define IGC_TARC0_CB_MULTIQ_3_REQ 0x30000000 97 #define IGC_TARC0_CB_MULTIQ_2_REQ 0x20000000 98 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL 99 100 #define IGC_ICH_RAR_ENTRIES 7 101 #define IGC_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */ 102 #define IGC_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */ 103 104 #define PHY_PAGE_SHIFT 5 105 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ 106 ((reg) & MAX_PHY_REG_ADDRESS)) 107 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ 108 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ 109 110 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 111 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 112 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 113 114 /* PHY Wakeup Registers and defines */ 115 #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17) 116 #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0) 117 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1) 118 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2) 119 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3) 120 #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) 121 #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) 122 #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) 123 #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) 124 #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) 125 126 #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */ 127 #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */ 128 #define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */ 129 #define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */ 130 #define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */ 131 #define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */ 132 #define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */ 133 134 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ 135 #define HV_MUX_DATA_CTRL PHY_REG(776, 16) 136 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 137 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 138 #define HV_STATS_PAGE 778 139 /* Half-duplex collision counts */ 140 #define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision */ 141 #define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17) 142 #define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. */ 143 #define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19) 144 #define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Collision */ 145 #define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21) 146 #define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision */ 147 #define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24) 148 #define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision */ 149 #define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26) 150 #define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */ 151 #define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28) 152 #define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */ 153 #define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30) 154 155 #define IGC_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ 156 157 #define IGC_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ 158 #define IGC_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ 159 #define K1_ENTRY_LATENCY 0 160 #define K1_MIN_TIME 1 161 162 /* SMBus Control Phy Register */ 163 #define CV_SMB_CTRL PHY_REG(769, 23) 164 #define CV_SMB_CTRL_FORCE_SMBUS 0x0001 165 166 /* I218 Ultra Low Power Configuration 1 Register */ 167 #define I218_ULP_CONFIG1 PHY_REG(779, 16) 168 #define I218_ULP_CONFIG1_START 0x0001 /* Start auto ULP config */ 169 #define I218_ULP_CONFIG1_IND 0x0004 /* Pwr up from ULP indication */ 170 #define I218_ULP_CONFIG1_STICKY_ULP 0x0010 /* Set sticky ULP mode */ 171 #define I218_ULP_CONFIG1_INBAND_EXIT 0x0020 /* Inband on ULP exit */ 172 #define I218_ULP_CONFIG1_WOL_HOST 0x0040 /* WoL Host on ULP exit */ 173 #define I218_ULP_CONFIG1_RESET_TO_SMBUS 0x0100 /* Reset to SMBus mode */ 174 /* enable ULP even if when phy powered down via lanphypc */ 175 #define I218_ULP_CONFIG1_EN_ULP_LANPHYPC 0x0400 176 /* disable clear of sticky ULP on PERST */ 177 #define I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST 0x0800 178 #define I218_ULP_CONFIG1_DISABLE_SMB_PERST 0x1000 /* Disable on PERST# */ 179 180 181 /* SMBus Address Phy Register */ 182 #define HV_SMB_ADDR PHY_REG(768, 26) 183 #define HV_SMB_ADDR_MASK 0x007F 184 #define HV_SMB_ADDR_PEC_EN 0x0200 185 #define HV_SMB_ADDR_VALID 0x0080 186 #define HV_SMB_ADDR_FREQ_MASK 0x1100 187 #define HV_SMB_ADDR_FREQ_LOW_SHIFT 8 188 #define HV_SMB_ADDR_FREQ_HIGH_SHIFT 12 189 190 /* Strapping Option Register - RO */ 191 #define IGC_STRAP 0x0000C 192 #define IGC_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000 193 #define IGC_STRAP_SMBUS_ADDRESS_SHIFT 17 194 #define IGC_STRAP_SMT_FREQ_MASK 0x00003000 195 #define IGC_STRAP_SMT_FREQ_SHIFT 12 196 197 /* OEM Bits Phy Register */ 198 #define HV_OEM_BITS PHY_REG(768, 25) 199 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */ 200 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ 201 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ 202 203 /* KMRN Mode Control */ 204 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16) 205 #define HV_KMRN_MDIO_SLOW 0x0400 206 207 /* KMRN FIFO Control and Status */ 208 #define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16) 209 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000 210 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12 211 212 /* PHY Power Management Control */ 213 #define HV_PM_CTRL PHY_REG(770, 17) 214 #define HV_PM_CTRL_K1_CLK_REQ 0x200 215 #define HV_PM_CTRL_K1_ENABLE 0x4000 216 217 #define I217_PLL_CLOCK_GATE_REG PHY_REG(772, 28) 218 #define I217_PLL_CLOCK_GATE_MASK 0x07FF 219 220 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */ 221 222 /* Inband Control */ 223 #define I217_INBAND_CTRL PHY_REG(770, 18) 224 #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK 0x3F00 225 #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT 8 226 227 /* Low Power Idle GPIO Control */ 228 #define I217_LPI_GPIO_CTRL PHY_REG(772, 18) 229 #define I217_LPI_GPIO_CTRL_AUTO_EN_LPI 0x0800 230 231 /* PHY Low Power Idle Control */ 232 #define I82579_LPI_CTRL PHY_REG(772, 20) 233 #define I82579_LPI_CTRL_100_ENABLE 0x2000 234 #define I82579_LPI_CTRL_1000_ENABLE 0x4000 235 #define I82579_LPI_CTRL_ENABLE_MASK 0x6000 236 237 /* 82579 DFT Control */ 238 #define I82579_DFT_CTRL PHY_REG(769, 20) 239 #define I82579_DFT_CTRL_GATE_PHY_RESET 0x0040 /* Gate PHY Reset on MAC Reset */ 240 241 /* Extended Management Interface (EMI) Registers */ 242 #define I82579_EMI_ADDR 0x10 243 #define I82579_EMI_DATA 0x11 244 #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */ 245 #define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */ 246 #define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */ 247 #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */ 248 #define I82579_RX_CONFIG 0x3412 /* Receive configuration */ 249 #define I82579_LPI_PLL_SHUT 0x4412 /* LPI PLL Shut Enable */ 250 #define I82579_EEE_PCS_STATUS 0x182E /* IEEE MMD Register 3.1 >> 8 */ 251 #define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */ 252 #define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */ 253 #define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */ 254 #define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE */ 255 #define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE */ 256 #define I82579_LPI_100_PLL_SHUT (1 << 2) /* 100M LPI PLL Shut Enabled */ 257 #define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */ 258 #define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */ 259 #define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */ 260 #define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */ 261 #define I217_RX_CONFIG 0xB20C /* Receive configuration */ 262 263 #define IGC_EEE_RX_LPI_RCVD 0x0400 /* Tx LP idle received */ 264 #define IGC_EEE_TX_LPI_RCVD 0x0800 /* Rx LP idle received */ 265 266 /* Intel Rapid Start Technology Support */ 267 #define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70) 268 #define I217_PROXY_CTRL_AUTO_DISABLE 0x0080 269 #define I217_CGFREG PHY_REG(772, 29) 270 #define I217_CGFREG_ENABLE_MTA_RESET 0x0002 271 #define I217_MEMPWR PHY_REG(772, 26) 272 #define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010 273 274 /* Receive Address Initial CRC Calculation */ 275 #define IGC_PCH_RAICC(_n) (0x05F50 + ((_n) * 4)) 276 277 #define IGC_PCI_VENDOR_ID_REGISTER 0x00 278 279 #define IGC_PCI_REVISION_ID_REG 0x08 280 void igc_set_kmrn_lock_loss_workaround_ich8lan(struct igc_hw *hw, 281 bool state); 282 void igc_igp3_phy_powerdown_workaround_ich8lan(struct igc_hw *hw); 283 void igc_gig_downshift_workaround_ich8lan(struct igc_hw *hw); 284 void igc_suspend_workarounds_ich8lan(struct igc_hw *hw); 285 u32 igc_resume_workarounds_pchlan(struct igc_hw *hw); 286 s32 igc_configure_k1_ich8lan(struct igc_hw *hw, bool k1_enable); 287 s32 igc_configure_k0s_lpt(struct igc_hw *hw, u8 entry_latency, u8 min_time); 288 void igc_copy_rx_addrs_to_phy_ich8lan(struct igc_hw *hw); 289 s32 igc_lv_jumbo_workaround_ich8lan(struct igc_hw *hw, bool enable); 290 s32 igc_read_emi_reg_locked(struct igc_hw *hw, u16 addr, u16 *data); 291 s32 igc_write_emi_reg_locked(struct igc_hw *hw, u16 addr, u16 data); 292 s32 igc_set_eee_pchlan(struct igc_hw *hw); 293 s32 igc_enable_ulp_lpt_lp(struct igc_hw *hw, bool to_sx); 294 s32 igc_disable_ulp_lpt_lp(struct igc_hw *hw, bool force); 295 #endif /* _IGC_ICH8LAN_H_ */ 296 void igc_demote_ltr(struct igc_hw *hw, bool demote, bool link); 297