1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #ifndef _IGC_DEFINES_H_ 6 #define _IGC_DEFINES_H_ 7 8 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 9 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 10 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 11 12 /* Definitions for power management and wakeup registers */ 13 /* Wake Up Control */ 14 #define IGC_WUC_APME 0x00000001 /* APM Enable */ 15 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */ 16 #define IGC_WUC_PME_STATUS 0x00000004 /* PME Status */ 17 #define IGC_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 18 #define IGC_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ 19 20 /* Wake Up Filter Control */ 21 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 22 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 23 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 24 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 25 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 26 #define IGC_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 27 #define IGC_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 28 #define IGC_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 29 30 /* Wake Up Status */ 31 #define IGC_WUS_LNKC IGC_WUFC_LNKC 32 #define IGC_WUS_MAG IGC_WUFC_MAG 33 #define IGC_WUS_EX IGC_WUFC_EX 34 #define IGC_WUS_MC IGC_WUFC_MC 35 #define IGC_WUS_BC IGC_WUFC_BC 36 37 /* Extended Device Control */ 38 #define IGC_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ 39 #define IGC_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */ 40 #define IGC_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */ 41 #define IGC_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */ 42 /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */ 43 #define IGC_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ 44 #define IGC_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ 45 #define IGC_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */ 46 #define IGC_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */ 47 #define IGC_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 48 /* Physical Func Reset Done Indication */ 49 #define IGC_CTRL_EXT_PFRSTD 0x00004000 50 #define IGC_CTRL_EXT_SDLPE 0X00040000 /* SerDes Low Power Enable */ 51 #define IGC_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 52 #define IGC_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 53 #define IGC_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clk Gating */ 54 #define IGC_CTRL_EXT_LINK_MODE_MASK 0x00C00000 55 /* Offset of the link mode field in Ctrl Ext register */ 56 #define IGC_CTRL_EXT_LINK_MODE_OFFSET 22 57 #define IGC_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000 58 #define IGC_CTRL_EXT_LINK_MODE_GMII 0x00000000 59 #define IGC_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 60 #define IGC_CTRL_EXT_LINK_MODE_SGMII 0x00800000 61 #define IGC_CTRL_EXT_EIAME 0x01000000 62 #define IGC_CTRL_EXT_IRCA 0x00000001 63 #define IGC_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */ 64 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */ 65 #define IGC_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 66 #define IGC_CTRL_EXT_LSECCK 0x00001000 67 #define IGC_CTRL_EXT_PHYPDEN 0x00100000 68 #define IGC_I2CCMD_REG_ADDR_SHIFT 16 69 #define IGC_I2CCMD_PHY_ADDR_SHIFT 24 70 #define IGC_I2CCMD_OPCODE_READ 0x08000000 71 #define IGC_I2CCMD_OPCODE_WRITE 0x00000000 72 #define IGC_I2CCMD_READY 0x20000000 73 #define IGC_I2CCMD_ERROR 0x80000000 74 #define IGC_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a)) 75 #define IGC_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a)) 76 #define IGC_MAX_SGMII_PHY_REG_ADDR 255 77 #define IGC_I2CCMD_PHY_TIMEOUT 200 78 #define IGC_IVAR_VALID 0x80 79 #define IGC_GPIE_NSICR 0x00000001 80 #define IGC_GPIE_MSIX_MODE 0x00000010 81 #define IGC_GPIE_EIAME 0x40000000 82 #define IGC_GPIE_PBA 0x80000000 83 84 /* Receive Descriptor bit definitions */ 85 #define IGC_RXD_STAT_DD 0x01 /* Descriptor Done */ 86 #define IGC_RXD_STAT_EOP 0x02 /* End of Packet */ 87 #define IGC_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 88 #define IGC_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 89 #define IGC_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 90 #define IGC_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 91 #define IGC_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 92 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 93 #define IGC_RXD_STAT_IPIDV 0x200 /* IP identification valid */ 94 #define IGC_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 95 #define IGC_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 96 #define IGC_RXD_ERR_CE 0x01 /* CRC Error */ 97 #define IGC_RXD_ERR_SE 0x02 /* Symbol Error */ 98 #define IGC_RXD_ERR_SEQ 0x04 /* Sequence Error */ 99 #define IGC_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 100 #define IGC_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 101 #define IGC_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 102 #define IGC_RXD_ERR_RXE 0x80 /* Rx Data Error */ 103 #define IGC_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 104 105 #define IGC_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */ 106 #define IGC_RXDEXT_STATERR_LB 0x00040000 107 #define IGC_RXDEXT_STATERR_CE 0x01000000 108 #define IGC_RXDEXT_STATERR_SE 0x02000000 109 #define IGC_RXDEXT_STATERR_SEQ 0x04000000 110 #define IGC_RXDEXT_STATERR_CXE 0x10000000 111 #define IGC_RXDEXT_STATERR_TCPE 0x20000000 112 #define IGC_RXDEXT_STATERR_IPE 0x40000000 113 #define IGC_RXDEXT_STATERR_RXE 0x80000000 114 115 /* mask to determine if packets should be dropped due to frame errors */ 116 #define IGC_RXD_ERR_FRAME_ERR_MASK ( \ 117 IGC_RXD_ERR_CE | \ 118 IGC_RXD_ERR_SE | \ 119 IGC_RXD_ERR_SEQ | \ 120 IGC_RXD_ERR_CXE | \ 121 IGC_RXD_ERR_RXE) 122 123 /* Same mask, but for extended and packet split descriptors */ 124 #define IGC_RXDEXT_ERR_FRAME_ERR_MASK ( \ 125 IGC_RXDEXT_STATERR_CE | \ 126 IGC_RXDEXT_STATERR_SE | \ 127 IGC_RXDEXT_STATERR_SEQ | \ 128 IGC_RXDEXT_STATERR_CXE | \ 129 IGC_RXDEXT_STATERR_RXE) 130 131 #define IGC_MRQC_ENABLE_RSS_2Q 0x00000001 132 #define IGC_MRQC_RSS_FIELD_MASK 0xFFFF0000 133 #define IGC_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 134 #define IGC_MRQC_RSS_FIELD_IPV4 0x00020000 135 #define IGC_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 136 #define IGC_MRQC_RSS_FIELD_IPV6 0x00100000 137 #define IGC_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 138 139 #define IGC_RXDPS_HDRSTAT_HDRSP 0x00008000 140 141 /* Management Control */ 142 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 143 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 144 #define IGC_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 145 #define IGC_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 146 #define IGC_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 147 /* Enable MAC address filtering */ 148 #define IGC_MANC_EN_MAC_ADDR_FILTER 0x00100000 149 /* Enable MNG packets to host memory */ 150 #define IGC_MANC_EN_MNG2HOST 0x00200000 151 152 #define IGC_MANC2H_PORT_623 0x00000020 /* Port 0x26f */ 153 #define IGC_MANC2H_PORT_664 0x00000040 /* Port 0x298 */ 154 #define IGC_MDEF_PORT_623 0x00000800 /* Port 0x26f */ 155 #define IGC_MDEF_PORT_664 0x00000400 /* Port 0x298 */ 156 157 /* Receive Control */ 158 #define IGC_RCTL_RST 0x00000001 /* Software reset */ 159 #define IGC_RCTL_EN 0x00000002 /* enable */ 160 #define IGC_RCTL_SBP 0x00000004 /* store bad packet */ 161 #define IGC_RCTL_UPE 0x00000008 /* unicast promisc enable */ 162 #define IGC_RCTL_MPE 0x00000010 /* multicast promisc enable */ 163 #define IGC_RCTL_LPE 0x00000020 /* long packet enable */ 164 #define IGC_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 165 #define IGC_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 166 #define IGC_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 167 #define IGC_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 168 #define IGC_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */ 169 #define IGC_RCTL_RDMTS_HEX 0x00010000 170 #define IGC_RCTL_RDMTS1_HEX IGC_RCTL_RDMTS_HEX 171 #define IGC_RCTL_MO_SHIFT 12 /* multicast offset shift */ 172 #define IGC_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 173 #define IGC_RCTL_BAM 0x00008000 /* broadcast enable */ 174 /* these buffer sizes are valid if IGC_RCTL_BSEX is 0 */ 175 #define IGC_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ 176 #define IGC_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ 177 #define IGC_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ 178 #define IGC_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ 179 /* these buffer sizes are valid if IGC_RCTL_BSEX is 1 */ 180 #define IGC_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */ 181 #define IGC_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */ 182 #define IGC_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */ 183 #define IGC_RCTL_VFE 0x00040000 /* vlan filter enable */ 184 #define IGC_RCTL_CFIEN 0x00080000 /* canonical form enable */ 185 #define IGC_RCTL_CFI 0x00100000 /* canonical form indicator */ 186 #define IGC_RCTL_DPF 0x00400000 /* discard pause frames */ 187 #define IGC_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 188 #define IGC_RCTL_BSEX 0x02000000 /* Buffer size extension */ 189 #define IGC_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 190 191 /* Use byte values for the following shift parameters 192 * Usage: 193 * psrctl |= (((ROUNDUP(value0, 128) >> IGC_PSRCTL_BSIZE0_SHIFT) & 194 * IGC_PSRCTL_BSIZE0_MASK) | 195 * ((ROUNDUP(value1, 1024) >> IGC_PSRCTL_BSIZE1_SHIFT) & 196 * IGC_PSRCTL_BSIZE1_MASK) | 197 * ((ROUNDUP(value2, 1024) << IGC_PSRCTL_BSIZE2_SHIFT) & 198 * IGC_PSRCTL_BSIZE2_MASK) | 199 * ((ROUNDUP(value3, 1024) << IGC_PSRCTL_BSIZE3_SHIFT) |; 200 * IGC_PSRCTL_BSIZE3_MASK)) 201 * where value0 = [128..16256], default=256 202 * value1 = [1024..64512], default=4096 203 * value2 = [0..64512], default=4096 204 * value3 = [0..64512], default=0 205 */ 206 207 #define IGC_PSRCTL_BSIZE0_MASK 0x0000007F 208 #define IGC_PSRCTL_BSIZE1_MASK 0x00003F00 209 #define IGC_PSRCTL_BSIZE2_MASK 0x003F0000 210 #define IGC_PSRCTL_BSIZE3_MASK 0x3F000000 211 212 #define IGC_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 213 #define IGC_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 214 #define IGC_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 215 #define IGC_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 216 217 /* SWFW_SYNC Definitions */ 218 #define IGC_SWFW_EEP_SM 0x01 219 #define IGC_SWFW_PHY0_SM 0x02 220 #define IGC_SWFW_PHY1_SM 0x04 221 #define IGC_SWFW_CSR_SM 0x08 222 #define IGC_SWFW_PHY2_SM 0x20 223 #define IGC_SWFW_PHY3_SM 0x40 224 #define IGC_SWFW_SW_MNG_SM 0x400 225 226 /* Device Control */ 227 #define IGC_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 228 #define IGC_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 229 #define IGC_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */ 230 #define IGC_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 231 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 232 #define IGC_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 233 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 234 #define IGC_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 235 #define IGC_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 236 #define IGC_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 237 #define IGC_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 238 #define IGC_CTRL_FRCSPD 0x00000800 /* Force Speed */ 239 #define IGC_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 240 #define IGC_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ 241 #define IGC_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ 242 #define IGC_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */ 243 #define IGC_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 244 #define IGC_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 245 #define IGC_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 246 #define IGC_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ 247 #define IGC_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */ 248 #define IGC_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 249 #define IGC_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 250 #define IGC_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ 251 #define IGC_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ 252 #define IGC_CTRL_DEV_RST 0x20000000 /* Device reset */ 253 #define IGC_CTRL_RST 0x04000000 /* Global reset */ 254 #define IGC_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 255 #define IGC_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 256 #define IGC_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 257 #define IGC_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 258 #define IGC_CTRL_I2C_ENA 0x02000000 /* I2C enable */ 259 260 #define IGC_CTRL_MDIO_DIR IGC_CTRL_SWDPIO2 261 #define IGC_CTRL_MDIO IGC_CTRL_SWDPIN2 262 #define IGC_CTRL_MDC_DIR IGC_CTRL_SWDPIO3 263 #define IGC_CTRL_MDC IGC_CTRL_SWDPIN3 264 265 #define IGC_CONNSW_AUTOSENSE_EN 0x1 266 #define IGC_CONNSW_ENRGSRC 0x4 267 #define IGC_CONNSW_PHYSD 0x400 268 #define IGC_CONNSW_PHY_PDN 0x800 269 #define IGC_CONNSW_SERDESD 0x200 270 #define IGC_CONNSW_AUTOSENSE_CONF 0x2 271 #define IGC_PCS_CFG_PCS_EN 8 272 #define IGC_PCS_LCTL_FLV_LINK_UP 1 273 #define IGC_PCS_LCTL_FSV_10 0 274 #define IGC_PCS_LCTL_FSV_100 2 275 #define IGC_PCS_LCTL_FSV_1000 4 276 #define IGC_PCS_LCTL_FDV_FULL 8 277 #define IGC_PCS_LCTL_FSD 0x10 278 #define IGC_PCS_LCTL_FORCE_LINK 0x20 279 #define IGC_PCS_LCTL_FORCE_FCTRL 0x80 280 #define IGC_PCS_LCTL_AN_ENABLE 0x10000 281 #define IGC_PCS_LCTL_AN_RESTART 0x20000 282 #define IGC_PCS_LCTL_AN_TIMEOUT 0x40000 283 #define IGC_ENABLE_SERDES_LOOPBACK 0x0410 284 285 #define IGC_PCS_LSTS_LINK_OK 1 286 #define IGC_PCS_LSTS_SPEED_100 2 287 #define IGC_PCS_LSTS_SPEED_1000 4 288 #define IGC_PCS_LSTS_DUPLEX_FULL 8 289 #define IGC_PCS_LSTS_SYNK_OK 0x10 290 #define IGC_PCS_LSTS_AN_COMPLETE 0x10000 291 292 /* Device Status */ 293 #define IGC_STATUS_FD 0x00000001 /* Duplex 0=half 1=full */ 294 #define IGC_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 295 #define IGC_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 296 #define IGC_STATUS_FUNC_SHIFT 2 297 #define IGC_STATUS_FUNC_1 0x00000004 /* Function 1 */ 298 #define IGC_STATUS_TXOFF 0x00000010 /* transmission paused */ 299 #define IGC_STATUS_SPEED_MASK 0x000000C0 300 #define IGC_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 301 #define IGC_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 302 #define IGC_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 303 /* Speed 2.5Gb/s indication for I225 */ 304 #define IGC_STATUS_SPEED_2500 0x00400000 305 #define IGC_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */ 306 #define IGC_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ 307 #define IGC_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */ 308 #define IGC_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ 309 #define IGC_STATUS_BUS64 0x00001000 /* In 64 bit slot */ 310 #define IGC_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */ 311 #define IGC_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */ 312 #define IGC_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ 313 #define IGC_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ 314 315 /* Constants used to interpret the masked PCI-X bus speed. */ 316 #define IGC_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */ 317 #define IGC_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */ 318 #define IGC_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/ 319 #define IGC_STATUS_PCIM_STATE 0x40000000 /* PCIm function state */ 320 321 #define SPEED_10 10 322 #define SPEED_100 100 323 #define SPEED_1000 1000 324 #define SPEED_2500 2500 325 #define HALF_DUPLEX 1 326 #define FULL_DUPLEX 2 327 328 #define PHY_FORCE_TIME 20 329 330 #define ADVERTISE_10_HALF 0x0001 331 #define ADVERTISE_10_FULL 0x0002 332 #define ADVERTISE_100_HALF 0x0004 333 #define ADVERTISE_100_FULL 0x0008 334 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 335 #define ADVERTISE_1000_FULL 0x0020 336 #define ADVERTISE_2500_HALF 0x0040 /* NOT used, just FYI */ 337 #define ADVERTISE_2500_FULL 0x0080 338 339 /* 1000/H is not supported, nor spec-compliant. */ 340 #define IGC_ALL_SPEED_DUPLEX ( \ 341 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 342 ADVERTISE_100_FULL | ADVERTISE_1000_FULL) 343 #define IGC_ALL_SPEED_DUPLEX_2500 ( \ 344 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 345 ADVERTISE_100_FULL | ADVERTISE_1000_FULL | ADVERTISE_2500_FULL) 346 #define IGC_ALL_NOT_GIG ( \ 347 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 348 ADVERTISE_100_FULL) 349 #define IGC_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 350 #define IGC_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 351 #define IGC_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 352 353 #define AUTONEG_ADVERTISE_SPEED_DEFAULT IGC_ALL_SPEED_DUPLEX 354 #define AUTONEG_ADVERTISE_SPEED_DEFAULT_2500 IGC_ALL_SPEED_DUPLEX_2500 355 356 /* LED Control */ 357 #define IGC_PHY_LED0_MODE_MASK 0x00000007 358 #define IGC_PHY_LED0_IVRT 0x00000008 359 #define IGC_PHY_LED0_MASK 0x0000001F 360 361 #define IGC_LEDCTL_LED0_MODE_MASK 0x0000000F 362 #define IGC_LEDCTL_LED0_MODE_SHIFT 0 363 #define IGC_LEDCTL_LED0_IVRT 0x00000040 364 #define IGC_LEDCTL_LED0_BLINK 0x00000080 365 366 #define IGC_LEDCTL_MODE_LINK_UP 0x2 367 #define IGC_LEDCTL_MODE_LED_ON 0xE 368 #define IGC_LEDCTL_MODE_LED_OFF 0xF 369 370 /* Transmit Descriptor bit definitions */ 371 #define IGC_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 372 #define IGC_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 373 #define IGC_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 374 #define IGC_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 375 #define IGC_TXD_CMD_EOP 0x01000000 /* End of Packet */ 376 #define IGC_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 377 #define IGC_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 378 #define IGC_TXD_CMD_RS 0x08000000 /* Report Status */ 379 #define IGC_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 380 #define IGC_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */ 381 #define IGC_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 382 #define IGC_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 383 #define IGC_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 384 #define IGC_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 385 #define IGC_TXD_STAT_LC 0x00000004 /* Late Collisions */ 386 #define IGC_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 387 #define IGC_TXD_CMD_TCP 0x01000000 /* TCP packet */ 388 #define IGC_TXD_CMD_IP 0x02000000 /* IP packet */ 389 #define IGC_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 390 #define IGC_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 391 #define IGC_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ 392 393 /* Transmit Control */ 394 #define IGC_TCTL_EN 0x00000002 /* enable Tx */ 395 #define IGC_TCTL_PSP 0x00000008 /* pad short packets */ 396 #define IGC_TCTL_CT 0x00000ff0 /* collision threshold */ 397 #define IGC_TCTL_COLD 0x003ff000 /* collision distance */ 398 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 399 #define IGC_TCTL_MULR 0x10000000 /* Multiple request support */ 400 401 /* Transmit Arbitration Count */ 402 #define IGC_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */ 403 404 /* SerDes Control */ 405 #define IGC_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 406 #define IGC_SCTL_ENABLE_SERDES_LOOPBACK 0x0410 407 408 /* Receive Checksum Control */ 409 #define IGC_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 410 #define IGC_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 411 #define IGC_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ 412 #define IGC_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 413 #define IGC_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 414 415 /* GPY211 - I225 defines */ 416 #define GPY_MMD_MASK 0xFFFF0000 417 #define GPY_MMD_SHIFT 16 418 #define GPY_REG_MASK 0x0000FFFF 419 /* Header split receive */ 420 #define IGC_RFCTL_NFSW_DIS 0x00000040 421 #define IGC_RFCTL_NFSR_DIS 0x00000080 422 #define IGC_RFCTL_ACK_DIS 0x00001000 423 #define IGC_RFCTL_EXTEN 0x00008000 424 #define IGC_RFCTL_IPV6_EX_DIS 0x00010000 425 #define IGC_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 426 #define IGC_RFCTL_LEF 0x00040000 427 428 /* Collision related configuration parameters */ 429 #define IGC_CT_SHIFT 4 430 #define IGC_COLLISION_THRESHOLD 15 431 #define IGC_COLLISION_DISTANCE 63 432 #define IGC_COLD_SHIFT 12 433 434 /* Default values for the transmit IPG register */ 435 #define DEFAULT_82542_TIPG_IPGT 10 436 #define DEFAULT_82543_TIPG_IPGT_FIBER 9 437 #define DEFAULT_82543_TIPG_IPGT_COPPER 8 438 439 #define IGC_TIPG_IPGT_MASK 0x000003FF 440 441 #define DEFAULT_82542_TIPG_IPGR1 2 442 #define DEFAULT_82543_TIPG_IPGR1 8 443 #define IGC_TIPG_IPGR1_SHIFT 10 444 445 #define DEFAULT_82542_TIPG_IPGR2 10 446 #define DEFAULT_82543_TIPG_IPGR2 6 447 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 448 #define IGC_TIPG_IPGR2_SHIFT 20 449 450 /* Ethertype field values */ 451 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 452 453 #define ETHERNET_FCS_SIZE 4 454 #define MAX_JUMBO_FRAME_SIZE 0x3F00 455 /* The datasheet maximum supported RX size is 9.5KB (9728 bytes) */ 456 #define MAX_RX_JUMBO_FRAME_SIZE 0x2600 457 #define IGC_TX_PTR_GAP 0x1F 458 459 /* Extended Configuration Control and Size */ 460 #define IGC_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 461 #define IGC_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 462 #define IGC_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 463 #define IGC_EXTCNF_CTRL_SWFLAG 0x00000020 464 #define IGC_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080 465 #define IGC_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 466 #define IGC_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 467 #define IGC_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 468 #define IGC_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 469 470 #define IGC_PHY_CTRL_D0A_LPLU 0x00000002 471 #define IGC_PHY_CTRL_NOND0A_LPLU 0x00000004 472 #define IGC_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 473 #define IGC_PHY_CTRL_GBE_DISABLE 0x00000040 474 475 #define IGC_KABGTXD_BGSQLBIAS 0x00050000 476 477 /* Low Power IDLE Control */ 478 #define IGC_LPIC_LPIET_SHIFT 24 /* Low Power Idle Entry Time */ 479 480 /* PBA constants */ 481 #define IGC_PBA_8K 0x0008 /* 8KB */ 482 #define IGC_PBA_10K 0x000A /* 10KB */ 483 #define IGC_PBA_12K 0x000C /* 12KB */ 484 #define IGC_PBA_14K 0x000E /* 14KB */ 485 #define IGC_PBA_16K 0x0010 /* 16KB */ 486 #define IGC_PBA_18K 0x0012 487 #define IGC_PBA_20K 0x0014 488 #define IGC_PBA_22K 0x0016 489 #define IGC_PBA_24K 0x0018 490 #define IGC_PBA_26K 0x001A 491 #define IGC_PBA_30K 0x001E 492 #define IGC_PBA_32K 0x0020 493 #define IGC_PBA_34K 0x0022 494 #define IGC_PBA_35K 0x0023 495 #define IGC_PBA_38K 0x0026 496 #define IGC_PBA_40K 0x0028 497 #define IGC_PBA_48K 0x0030 /* 48KB */ 498 #define IGC_PBA_64K 0x0040 /* 64KB */ 499 500 #define IGC_PBA_RXA_MASK 0xFFFF 501 502 #define IGC_PBS_16K IGC_PBA_16K 503 504 /* Uncorrectable/correctable ECC Error counts and enable bits */ 505 #define IGC_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF 506 #define IGC_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00 507 #define IGC_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8 508 #define IGC_PBECCSTS_ECC_ENABLE 0x00010000 509 510 #define IFS_MAX 80 511 #define IFS_MIN 40 512 #define IFS_RATIO 4 513 #define IFS_STEP 10 514 #define MIN_NUM_XMITS 1000 515 516 /* SW Semaphore Register */ 517 #define IGC_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 518 #define IGC_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 519 #define IGC_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 520 521 #define IGC_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ 522 523 /* Interrupt Cause Read */ 524 #define IGC_ICR_TXDW 0x00000001 /* Transmit desc written back */ 525 #define IGC_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 526 #define IGC_ICR_LSC 0x00000004 /* Link Status Change */ 527 #define IGC_ICR_RXSEQ 0x00000008 /* Rx sequence error */ 528 #define IGC_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ 529 #define IGC_ICR_RXO 0x00000040 /* Rx overrun */ 530 #define IGC_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ 531 #define IGC_ICR_VMMB 0x00000100 /* VM MB event */ 532 #define IGC_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */ 533 #define IGC_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 534 #define IGC_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 535 #define IGC_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 536 #define IGC_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 537 #define IGC_ICR_TXD_LOW 0x00008000 538 #define IGC_ICR_MNG 0x00040000 /* Manageability event */ 539 #define IGC_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */ 540 #define IGC_ICR_TS 0x00080000 /* Time Sync Interrupt */ 541 #define IGC_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ 542 /* If this bit asserted, the driver should claim the interrupt */ 543 #define IGC_ICR_INT_ASSERTED 0x80000000 544 #define IGC_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 545 #define IGC_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ 546 #define IGC_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ 547 #define IGC_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ 548 #define IGC_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ 549 #define IGC_ICR_OTHER 0x01000000 /* Other Interrupts */ 550 #define IGC_ICR_FER 0x00400000 /* Fatal Error */ 551 552 #define IGC_ICR_THS 0x00800000 /* ICR.THS: Thermal Sensor Event*/ 553 #define IGC_ICR_MDDET 0x10000000 /* Malicious Driver Detect */ 554 555 /* PBA ECC Register */ 556 #define IGC_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ 557 #define IGC_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ 558 #define IGC_PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */ 559 #define IGC_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 560 #define IGC_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */ 561 562 /* Extended Interrupt Cause Read */ 563 #define IGC_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ 564 #define IGC_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ 565 #define IGC_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ 566 #define IGC_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ 567 #define IGC_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ 568 #define IGC_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ 569 #define IGC_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ 570 #define IGC_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ 571 #define IGC_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 572 #define IGC_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 573 /* TCP Timer */ 574 #define IGC_TCPTIMER_KS 0x00000100 /* KickStart */ 575 #define IGC_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */ 576 #define IGC_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */ 577 #define IGC_TCPTIMER_LOOP 0x00000800 /* Loop */ 578 579 /* This defines the bits that are set in the Interrupt Mask 580 * Set/Read Register. Each bit is documented below: 581 * o RXT0 = Receiver Timer Interrupt (ring 0) 582 * o TXDW = Transmit Descriptor Written Back 583 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 584 * o RXSEQ = Receive Sequence Error 585 * o LSC = Link Status Change 586 */ 587 #define IMS_ENABLE_MASK ( \ 588 IGC_IMS_RXT0 | \ 589 IGC_IMS_TXDW | \ 590 IGC_IMS_RXDMT0 | \ 591 IGC_IMS_RXSEQ | \ 592 IGC_IMS_LSC) 593 594 /* Interrupt Mask Set */ 595 #define IGC_IMS_TXDW IGC_ICR_TXDW /* Tx desc written back */ 596 #define IGC_IMS_TXQE IGC_ICR_TXQE /* Transmit Queue empty */ 597 #define IGC_IMS_LSC IGC_ICR_LSC /* Link Status Change */ 598 #define IGC_IMS_VMMB IGC_ICR_VMMB /* Mail box activity */ 599 #define IGC_IMS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */ 600 #define IGC_IMS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */ 601 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */ 602 #define IGC_ITR_VAL_MASK 0x04 /* ITR value mask */ 603 #define IGC_IMS_RXO IGC_ICR_RXO /* Rx overrun */ 604 #define IGC_IMS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */ 605 #define IGC_IMS_TXD_LOW IGC_ICR_TXD_LOW 606 #define IGC_IMS_ECCER IGC_ICR_ECCER /* Uncorrectable ECC Error */ 607 #define IGC_IMS_TS IGC_ICR_TS /* Time Sync Interrupt */ 608 #define IGC_IMS_DRSTA IGC_ICR_DRSTA /* Device Reset Asserted */ 609 #define IGC_IMS_DOUTSYNC IGC_ICR_DOUTSYNC /* NIC DMA out of sync */ 610 #define IGC_IMS_RXQ0 IGC_ICR_RXQ0 /* Rx Queue 0 Interrupt */ 611 #define IGC_IMS_RXQ1 IGC_ICR_RXQ1 /* Rx Queue 1 Interrupt */ 612 #define IGC_IMS_TXQ0 IGC_ICR_TXQ0 /* Tx Queue 0 Interrupt */ 613 #define IGC_IMS_TXQ1 IGC_ICR_TXQ1 /* Tx Queue 1 Interrupt */ 614 #define IGC_IMS_OTHER IGC_ICR_OTHER /* Other Interrupts */ 615 #define IGC_IMS_FER IGC_ICR_FER /* Fatal Error */ 616 617 #define IGC_IMS_THS IGC_ICR_THS /* ICR.TS: Thermal Sensor Event*/ 618 #define IGC_IMS_MDDET IGC_ICR_MDDET /* Malicious Driver Detect */ 619 /* Extended Interrupt Mask Set */ 620 #define IGC_EIMS_RX_QUEUE0 IGC_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 621 #define IGC_EIMS_RX_QUEUE1 IGC_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 622 #define IGC_EIMS_RX_QUEUE2 IGC_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 623 #define IGC_EIMS_RX_QUEUE3 IGC_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 624 #define IGC_EIMS_TX_QUEUE0 IGC_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 625 #define IGC_EIMS_TX_QUEUE1 IGC_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ 626 #define IGC_EIMS_TX_QUEUE2 IGC_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ 627 #define IGC_EIMS_TX_QUEUE3 IGC_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ 628 #define IGC_EIMS_TCP_TIMER IGC_EICR_TCP_TIMER /* TCP Timer */ 629 #define IGC_EIMS_OTHER IGC_EICR_OTHER /* Interrupt Cause Active */ 630 631 /* Interrupt Cause Set */ 632 #define IGC_ICS_LSC IGC_ICR_LSC /* Link Status Change */ 633 #define IGC_ICS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */ 634 #define IGC_ICS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */ 635 #define IGC_ICS_DRSTA IGC_ICR_DRSTA /* Device Reset Aserted */ 636 637 /* Extended Interrupt Cause Set */ 638 #define IGC_EICS_RX_QUEUE0 IGC_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 639 #define IGC_EICS_RX_QUEUE1 IGC_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 640 #define IGC_EICS_RX_QUEUE2 IGC_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 641 #define IGC_EICS_RX_QUEUE3 IGC_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 642 #define IGC_EICS_TX_QUEUE0 IGC_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 643 #define IGC_EICS_TX_QUEUE1 IGC_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ 644 #define IGC_EICS_TX_QUEUE2 IGC_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ 645 #define IGC_EICS_TX_QUEUE3 IGC_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ 646 #define IGC_EICS_TCP_TIMER IGC_EICR_TCP_TIMER /* TCP Timer */ 647 #define IGC_EICS_OTHER IGC_EICR_OTHER /* Interrupt Cause Active */ 648 649 #define IGC_EITR_ITR_INT_MASK 0x0000FFFF 650 #define IGC_EITR_INTERVAL 0x00007FFC 651 /* IGC_EITR_CNT_IGNR is only for 82576 and newer */ 652 #define IGC_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ 653 654 /* Transmit Descriptor Control */ 655 #define IGC_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 656 #define IGC_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 657 #define IGC_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 658 #define IGC_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 659 #define IGC_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 660 #define IGC_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ 661 /* Enable the counting of descriptors still to be processed. */ 662 #define IGC_TXDCTL_COUNT_DESC 0x00400000 663 664 /* Flow Control Constants */ 665 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 666 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 667 #define FLOW_CONTROL_TYPE 0x8808 668 669 /* 802.1q VLAN Packet Size */ 670 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ 671 #define IGC_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 672 673 /* Receive Address 674 * Number of high/low register pairs in the RAR. The RAR (Receive Address 675 * Registers) holds the directed and multicast addresses that we monitor. 676 * Technically, we have 16 spots. However, we reserve one of these spots 677 * (RAR[15]) for our directed address used by controllers with 678 * manageability enabled, allowing us room for 15 multicast addresses. 679 */ 680 #define IGC_RAR_ENTRIES 15 681 #define IGC_RAH_AV 0x80000000 /* Receive descriptor valid */ 682 #define IGC_RAL_MAC_ADDR_LEN 4 683 #define IGC_RAH_MAC_ADDR_LEN 2 684 #define IGC_RAH_QUEUE_MASK_82575 0x000C0000 685 #define IGC_RAH_POOL_1 0x00040000 686 687 /* Error Codes */ 688 #define IGC_SUCCESS 0 689 #define IGC_ERR_NVM 1 690 #define IGC_ERR_PHY 2 691 #define IGC_ERR_CONFIG 3 692 #define IGC_ERR_PARAM 4 693 #define IGC_ERR_MAC_INIT 5 694 #define IGC_ERR_PHY_TYPE 6 695 #define IGC_ERR_RESET 9 696 #define IGC_ERR_MASTER_REQUESTS_PENDING 10 697 #define IGC_ERR_HOST_INTERFACE_COMMAND 11 698 #define IGC_BLK_PHY_RESET 12 699 #define IGC_ERR_SWFW_SYNC 13 700 #define IGC_NOT_IMPLEMENTED 14 701 #define IGC_ERR_MBX 15 702 #define IGC_ERR_INVALID_ARGUMENT 16 703 #define IGC_ERR_NO_SPACE 17 704 #define IGC_ERR_NVM_PBA_SECTION 18 705 #define IGC_ERR_I2C 19 706 #define IGC_ERR_INVM_VALUE_NOT_FOUND 20 707 708 /* Loop limit on how long we wait for auto-negotiation to complete */ 709 #define FIBER_LINK_UP_LIMIT 50 710 #define COPPER_LINK_UP_LIMIT 10 711 #define PHY_AUTO_NEG_LIMIT 45 712 #define PHY_FORCE_LIMIT 20 713 /* Number of 100 microseconds we wait for PCI Express master disable */ 714 #define MASTER_DISABLE_TIMEOUT 800 715 /* Number of milliseconds we wait for PHY configuration done after MAC reset */ 716 #define PHY_CFG_TIMEOUT 100 717 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 718 #define MDIO_OWNERSHIP_TIMEOUT 10 719 /* Number of milliseconds for NVM auto read done after MAC reset. */ 720 #define AUTO_READ_DONE_TIMEOUT 10 721 722 /* Flow Control */ 723 #define IGC_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 724 #define IGC_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 725 #define IGC_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 726 727 /* Transmit Configuration Word */ 728 #define IGC_TXCW_FD 0x00000020 /* TXCW full duplex */ 729 #define IGC_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 730 #define IGC_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 731 #define IGC_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 732 #define IGC_TXCW_ANE 0x80000000 /* Auto-neg enable */ 733 734 /* Receive Configuration Word */ 735 #define IGC_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 736 #define IGC_RXCW_IV 0x08000000 /* Receive config invalid */ 737 #define IGC_RXCW_C 0x20000000 /* Receive config */ 738 #define IGC_RXCW_SYNCH 0x40000000 /* Receive config synch */ 739 740 #define IGC_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ 741 #define IGC_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ 742 743 /* HH Time Sync */ 744 #define IGC_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000 /* max delay */ 745 #define IGC_TSYNCTXCTL_SYNC_COMP_ERR 0x20000000 /* sync err */ 746 #define IGC_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */ 747 #define IGC_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */ 748 749 #define IGC_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 750 #define IGC_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 751 #define IGC_TSYNCRXCTL_TYPE_L2_V2 0x00 752 #define IGC_TSYNCRXCTL_TYPE_L4_V1 0x02 753 #define IGC_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 754 #define IGC_TSYNCRXCTL_TYPE_ALL 0x08 755 #define IGC_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 756 #define IGC_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ 757 #define IGC_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */ 758 759 #define IGC_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000 760 #define IGC_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000 761 762 #define IGC_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000 763 #define IGC_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000 764 765 #define IGC_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF 766 #define IGC_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 767 #define IGC_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01 768 #define IGC_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02 769 #define IGC_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03 770 #define IGC_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04 771 772 #define IGC_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00 773 #define IGC_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000 774 #define IGC_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100 775 #define IGC_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200 776 #define IGC_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300 777 #define IGC_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800 778 #define IGC_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900 779 #define IGC_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00 780 #define IGC_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00 781 #define IGC_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00 782 #define IGC_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00 783 784 #define IGC_TIMINCA_16NS_SHIFT 24 785 #define IGC_TIMINCA_INCPERIOD_SHIFT 24 786 #define IGC_TIMINCA_INCVALUE_MASK 0x00FFFFFF 787 788 /* Time Sync Interrupt Cause/Mask Register Bits */ 789 #define TSINTR_SYS_WRAP (1 << 0) /* SYSTIM Wrap around. */ 790 #define TSINTR_TXTS (1 << 1) /* Transmit Timestamp. */ 791 #define TSINTR_TT0 (1 << 3) /* Target Time 0 Trigger. */ 792 #define TSINTR_TT1 (1 << 4) /* Target Time 1 Trigger. */ 793 #define TSINTR_AUTT0 (1 << 5) /* Auxiliary Timestamp 0 Taken. */ 794 #define TSINTR_AUTT1 (1 << 6) /* Auxiliary Timestamp 1 Taken. */ 795 796 #define TSYNC_INTERRUPTS TSINTR_TXTS 797 798 /* TSAUXC Configuration Bits */ 799 #define TSAUXC_EN_TT0 (1 << 0) /* Enable target time 0. */ 800 #define TSAUXC_EN_TT1 (1 << 1) /* Enable target time 1. */ 801 #define TSAUXC_EN_CLK0 (1 << 2) /* Enable Configurable Frequency Clock 0. */ 802 #define TSAUXC_ST0 (1 << 4) /* Start Clock 0 Toggle on Target Time 0. */ 803 #define TSAUXC_EN_CLK1 (1 << 5) /* Enable Configurable Frequency Clock 1. */ 804 #define TSAUXC_ST1 (1 << 7) /* Start Clock 1 Toggle on Target Time 1. */ 805 #define TSAUXC_EN_TS0 (1 << 8) /* Enable hardware timestamp 0. */ 806 #define TSAUXC_EN_TS1 (1 << 10) /* Enable hardware timestamp 0. */ 807 808 /* SDP Configuration Bits */ 809 #define AUX0_SEL_SDP0 (0u << 0) /* Assign SDP0 to auxiliary time stamp 0. */ 810 #define AUX0_SEL_SDP1 (1u << 0) /* Assign SDP1 to auxiliary time stamp 0. */ 811 #define AUX0_SEL_SDP2 (2u << 0) /* Assign SDP2 to auxiliary time stamp 0. */ 812 #define AUX0_SEL_SDP3 (3u << 0) /* Assign SDP3 to auxiliary time stamp 0. */ 813 #define AUX0_TS_SDP_EN (1u << 2) /* Enable auxiliary time stamp trigger 0. */ 814 #define AUX1_SEL_SDP0 (0u << 3) /* Assign SDP0 to auxiliary time stamp 1. */ 815 #define AUX1_SEL_SDP1 (1u << 3) /* Assign SDP1 to auxiliary time stamp 1. */ 816 #define AUX1_SEL_SDP2 (2u << 3) /* Assign SDP2 to auxiliary time stamp 1. */ 817 #define AUX1_SEL_SDP3 (3u << 3) /* Assign SDP3 to auxiliary time stamp 1. */ 818 #define AUX1_TS_SDP_EN (1u << 5) /* Enable auxiliary time stamp trigger 1. */ 819 #define TS_SDP0_EN (1u << 8) /* SDP0 is assigned to Tsync. */ 820 #define TS_SDP1_EN (1u << 11) /* SDP1 is assigned to Tsync. */ 821 #define TS_SDP2_EN (1u << 14) /* SDP2 is assigned to Tsync. */ 822 #define TS_SDP3_EN (1u << 17) /* SDP3 is assigned to Tsync. */ 823 #define TS_SDP0_SEL_TT0 (0u << 6) /* Target time 0 is output on SDP0. */ 824 #define TS_SDP0_SEL_TT1 (1u << 6) /* Target time 1 is output on SDP0. */ 825 #define TS_SDP1_SEL_TT0 (0u << 9) /* Target time 0 is output on SDP1. */ 826 #define TS_SDP1_SEL_TT1 (1u << 9) /* Target time 1 is output on SDP1. */ 827 #define TS_SDP0_SEL_FC0 (2u << 6) /* Freq clock 0 is output on SDP0. */ 828 #define TS_SDP0_SEL_FC1 (3u << 6) /* Freq clock 1 is output on SDP0. */ 829 #define TS_SDP1_SEL_FC0 (2u << 9) /* Freq clock 0 is output on SDP1. */ 830 #define TS_SDP1_SEL_FC1 (3u << 9) /* Freq clock 1 is output on SDP1. */ 831 #define TS_SDP2_SEL_TT0 (0u << 12) /* Target time 0 is output on SDP2. */ 832 #define TS_SDP2_SEL_TT1 (1u << 12) /* Target time 1 is output on SDP2. */ 833 #define TS_SDP2_SEL_FC0 (2u << 12) /* Freq clock 0 is output on SDP2. */ 834 #define TS_SDP2_SEL_FC1 (3u << 12) /* Freq clock 1 is output on SDP2. */ 835 #define TS_SDP3_SEL_TT0 (0u << 15) /* Target time 0 is output on SDP3. */ 836 #define TS_SDP3_SEL_TT1 (1u << 15) /* Target time 1 is output on SDP3. */ 837 #define TS_SDP3_SEL_FC0 (2u << 15) /* Freq clock 0 is output on SDP3. */ 838 #define TS_SDP3_SEL_FC1 (3u << 15) /* Freq clock 1 is output on SDP3. */ 839 840 #define IGC_CTRL_SDP0_DIR 0x00400000 /* SDP0 Data direction */ 841 #define IGC_CTRL_SDP1_DIR 0x00800000 /* SDP1 Data direction */ 842 843 /* Extended Device Control */ 844 #define IGC_CTRL_EXT_SDP2_DIR 0x00000400 /* SDP2 Data direction */ 845 846 /* ETQF register bit definitions */ 847 #define IGC_ETQF_1588 (1 << 30) 848 #define IGC_FTQF_VF_BP 0x00008000 849 #define IGC_FTQF_1588_TIME_STAMP 0x08000000 850 #define IGC_FTQF_MASK 0xF0000000 851 #define IGC_FTQF_MASK_PROTO_BP 0x10000000 852 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 853 #define IGC_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */ 854 #define IGC_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 855 856 #define IGC_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */ 857 #define IGC_TSICR_TXTS 0x00000002 858 #define IGC_TSIM_TXTS 0x00000002 859 /* TUPLE Filtering Configuration */ 860 #define IGC_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */ 861 #define IGC_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */ 862 #define IGC_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */ 863 /* TTQF TCP Bit, shift with IGC_TTQF_PROTOCOL SHIFT */ 864 #define IGC_TTQF_PROTOCOL_TCP 0x0 865 /* TTQF UDP Bit, shift with IGC_TTQF_PROTOCOL_SHIFT */ 866 #define IGC_TTQF_PROTOCOL_UDP 0x1 867 /* TTQF SCTP Bit, shift with IGC_TTQF_PROTOCOL_SHIFT */ 868 #define IGC_TTQF_PROTOCOL_SCTP 0x2 869 #define IGC_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */ 870 #define IGC_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */ 871 #define IGC_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */ 872 #define IGC_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */ 873 #define IGC_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */ 874 #define IGC_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */ 875 #define IGC_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */ 876 #define IGC_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */ 877 878 #define IGC_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */ 879 #define IGC_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */ 880 #define IGC_MDICNFG_PHY_MASK 0x03E00000 881 #define IGC_MDICNFG_PHY_SHIFT 21 882 883 #define IGC_MEDIA_PORT_COPPER 1 884 #define IGC_MEDIA_PORT_OTHER 2 885 #define IGC_M88E1112_AUTO_COPPER_SGMII 0x2 886 #define IGC_M88E1112_AUTO_COPPER_BASEX 0x3 887 #define IGC_M88E1112_STATUS_LINK 0x0004 /* Interface Link Bit */ 888 #define IGC_M88E1112_MAC_CTRL_1 0x10 889 #define IGC_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380 /* Mode Select */ 890 #define IGC_M88E1112_MAC_CTRL_1_MODE_SHIFT 7 891 #define IGC_M88E1112_PAGE_ADDR 0x16 892 #define IGC_M88E1112_STATUS 0x01 893 894 #define IGC_THSTAT_LOW_EVENT 0x20000000 /* Low thermal threshold */ 895 #define IGC_THSTAT_MID_EVENT 0x00200000 /* Mid thermal threshold */ 896 #define IGC_THSTAT_HIGH_EVENT 0x00002000 /* High thermal threshold */ 897 #define IGC_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */ 898 #define IGC_THSTAT_LINK_THROTTLE 0x00000002 /* Link Spd Throttle Event */ 899 900 /* EEE defines */ 901 #define IGC_IPCNFG_EEE_2_5G_AN 0x00000010 /* IPCNFG EEE Ena 2.5G AN */ 902 #define IGC_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */ 903 #define IGC_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */ 904 #define IGC_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */ 905 #define IGC_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */ 906 #define IGC_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */ 907 /* EEE status */ 908 #define IGC_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ 909 #define IGC_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */ 910 #define IGC_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */ 911 #define IGC_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */ 912 #define IGC_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */ 913 #define IGC_M88E1543_EEE_CTRL_1 0x0 914 #define IGC_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */ 915 #define IGC_M88E1543_FIBER_CTRL 0x0 /* Fiber Control Register */ 916 #define IGC_EEE_ADV_DEV_I354 7 917 #define IGC_EEE_ADV_ADDR_I354 60 918 #define IGC_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */ 919 #define IGC_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */ 920 #define IGC_PCS_STATUS_DEV_I354 3 921 #define IGC_PCS_STATUS_ADDR_I354 1 922 #define IGC_PCS_STATUS_RX_LPI_RCVD 0x0400 923 #define IGC_PCS_STATUS_TX_LPI_RCVD 0x0800 924 #define IGC_M88E1512_CFG_REG_1 0x0010 925 #define IGC_M88E1512_CFG_REG_2 0x0011 926 #define IGC_M88E1512_CFG_REG_3 0x0007 927 #define IGC_M88E1512_MODE 0x0014 928 #define IGC_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */ 929 #define IGC_EEE_LP_ADV_DEV_I210 7 /* EEE LP Adv Device */ 930 #define IGC_EEE_LP_ADV_ADDR_I210 61 /* EEE LP Adv Register */ 931 #define IGC_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */ 932 #define IGC_EEE_LP_ADV_DEV_I225 7 /* EEE LP Adv Device */ 933 #define IGC_EEE_LP_ADV_ADDR_I225 61 /* EEE LP Adv Register */ 934 935 /* PCI Express Control */ 936 #define IGC_GCR_RXD_NO_SNOOP 0x00000001 937 #define IGC_GCR_RXDSCW_NO_SNOOP 0x00000002 938 #define IGC_GCR_RXDSCR_NO_SNOOP 0x00000004 939 #define IGC_GCR_TXD_NO_SNOOP 0x00000008 940 #define IGC_GCR_TXDSCW_NO_SNOOP 0x00000010 941 #define IGC_GCR_TXDSCR_NO_SNOOP 0x00000020 942 #define IGC_GCR_CMPL_TMOUT_MASK 0x0000F000 943 #define IGC_GCR_CMPL_TMOUT_10ms 0x00001000 944 #define IGC_GCR_CMPL_TMOUT_RESEND 0x00010000 945 #define IGC_GCR_CAP_VER2 0x00040000 946 947 #define PCIE_NO_SNOOP_ALL (IGC_GCR_RXD_NO_SNOOP | \ 948 IGC_GCR_RXDSCW_NO_SNOOP | \ 949 IGC_GCR_RXDSCR_NO_SNOOP | \ 950 IGC_GCR_TXD_NO_SNOOP | \ 951 IGC_GCR_TXDSCW_NO_SNOOP | \ 952 IGC_GCR_TXDSCR_NO_SNOOP) 953 954 #define IGC_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */ 955 956 /* mPHY address control and data registers */ 957 #define IGC_MPHY_ADDR_CTL 0x0024 /* Address Control Reg */ 958 #define IGC_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000 959 #define IGC_MPHY_DATA 0x0E10 /* Data Register */ 960 961 /* AFE CSR Offset for PCS CLK */ 962 #define IGC_MPHY_PCS_CLK_REG_OFFSET 0x0004 963 /* Override for near end digital loopback. */ 964 #define IGC_MPHY_PCS_CLK_REG_DIGINELBEN 0x10 965 966 /* PHY Control Register */ 967 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 968 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 969 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 970 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 971 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 972 #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 973 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 974 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 975 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 976 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 977 #define MII_CR_SPEED_1000 0x0040 978 #define MII_CR_SPEED_100 0x2000 979 #define MII_CR_SPEED_10 0x0000 980 981 /* PHY Status Register */ 982 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 983 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 984 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 985 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 986 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 987 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 988 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 989 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 990 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 991 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 992 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 993 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 994 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 995 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 996 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 997 998 /* Autoneg Advertisement Register */ 999 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ 1000 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 1001 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 1002 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 1003 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 1004 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 1005 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 1006 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 1007 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 1008 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 1009 1010 /* Link Partner Ability Register (Base Page) */ 1011 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ 1012 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP 10T Half Dplx Capable */ 1013 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP 10T Full Dplx Capable */ 1014 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */ 1015 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */ 1016 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ 1017 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 1018 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asym Pause Direction bit */ 1019 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP detected Remote Fault */ 1020 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */ 1021 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 1022 1023 /* Autoneg Expansion Register */ 1024 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 1025 #define NWAY_ER_PAGE_RXD 0x0002 /* LP 10T Half Dplx Capable */ 1026 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP 10T Full Dplx Capable */ 1027 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */ 1028 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */ 1029 1030 /* 1000BASE-T Control Register */ 1031 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 1032 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 1033 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 1034 /* 1=Repeater/switch device port 0=DTE device */ 1035 #define CR_1000T_REPEATER_DTE 0x0400 1036 /* 1=Configure PHY as Master 0=Configure PHY as Slave */ 1037 #define CR_1000T_MS_VALUE 0x0800 1038 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ 1039 #define CR_1000T_MS_ENABLE 0x1000 1040 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 1041 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 1042 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 1043 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 1044 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 1045 1046 /* 1000BASE-T Status Register */ 1047 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle err since last rd */ 1048 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asym pause direction bit */ 1049 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 1050 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 1051 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 1052 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 1053 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */ 1054 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ 1055 1056 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 1057 1058 /* PHY 1000 MII Register/Bit Definitions */ 1059 /* PHY Registers defined by IEEE */ 1060 #define PHY_CONTROL 0x00 /* Control Register */ 1061 #define PHY_STATUS 0x01 /* Status Register */ 1062 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 1063 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 1064 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 1065 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 1066 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 1067 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */ 1068 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 1069 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 1070 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 1071 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 1072 1073 /* PHY GPY 211 registers */ 1074 #define STANDARD_AN_REG_MASK 0x0007 /* MMD */ 1075 #define ANEG_MULTIGBT_AN_CTRL 0x0020 /* MULTI GBT AN Control Register */ 1076 #define MMD_DEVADDR_SHIFT 16 /* Shift MMD to higher bits */ 1077 #define CR_2500T_FD_CAPS 0x0080 /* Advertise 2500T FD capability */ 1078 1079 #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */ 1080 1081 /* NVM Control */ 1082 #define IGC_EECD_SK 0x00000001 /* NVM Clock */ 1083 #define IGC_EECD_CS 0x00000002 /* NVM Chip Select */ 1084 #define IGC_EECD_DI 0x00000004 /* NVM Data In */ 1085 #define IGC_EECD_DO 0x00000008 /* NVM Data Out */ 1086 #define IGC_EECD_REQ 0x00000040 /* NVM Access Request */ 1087 #define IGC_EECD_GNT 0x00000080 /* NVM Access Grant */ 1088 #define IGC_EECD_PRES 0x00000100 /* NVM Present */ 1089 #define IGC_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ 1090 #define IGC_EECD_BLOCKED 0x00008000 /* Bit banging access blocked flag */ 1091 #define IGC_EECD_ABORT 0x00010000 /* NVM operation aborted flag */ 1092 #define IGC_EECD_TIMEOUT 0x00020000 /* NVM read operation timeout flag */ 1093 #define IGC_EECD_ERROR_CLR 0x00040000 /* NVM error status clear bit */ 1094 /* NVM Addressing bits based on type 0=small, 1=large */ 1095 #define IGC_EECD_ADDR_BITS 0x00000400 1096 #define IGC_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */ 1097 #define IGC_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 1098 #define IGC_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 1099 #define IGC_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 1100 #define IGC_EECD_SIZE_EX_SHIFT 11 1101 #define IGC_EECD_FLUPD 0x00080000 /* Update FLASH */ 1102 #define IGC_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */ 1103 #define IGC_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 1104 #define IGC_EECD_SEC1VAL_VALID_MASK (IGC_EECD_AUTO_RD | IGC_EECD_PRES) 1105 #define IGC_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ 1106 #define IGC_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done */ 1107 #define IGC_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */ 1108 #define IGC_EECD_SEC1VAL_I210 0x02000000 /* Sector One Valid */ 1109 #define IGC_FLUDONE_ATTEMPTS 20000 1110 #define IGC_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 1111 #define IGC_I210_FIFO_SEL_RX 0x00 1112 #define IGC_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) 1113 #define IGC_I210_FIFO_SEL_TX_LEGACY IGC_I210_FIFO_SEL_TX_QAV(0) 1114 #define IGC_I210_FIFO_SEL_BMC2OS_TX 0x06 1115 #define IGC_I210_FIFO_SEL_BMC2OS_RX 0x01 1116 1117 #define IGC_I210_FLASH_SECTOR_SIZE 0x1000 /* 4KB FLASH sector unit size */ 1118 /* Secure FLASH mode requires removing MSb */ 1119 #define IGC_I210_FW_PTR_MASK 0x7FFF 1120 /* Firmware code revision field word offset*/ 1121 #define IGC_I210_FW_VER_OFFSET 328 1122 1123 #define IGC_EECD_FLUPD_I225 0x00800000 /* Update FLASH */ 1124 #define IGC_EECD_FLUDONE_I225 0x04000000 /* Update FLASH done */ 1125 #define IGC_EECD_FLASH_DETECTED_I225 0x00080000 /* FLASH detected */ 1126 #define IGC_FLUDONE_ATTEMPTS 20000 1127 #define IGC_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 1128 #define IGC_EECD_SEC1VAL_I225 0x02000000 /* Sector One Valid */ 1129 #define IGC_FLSECU_BLK_SW_ACCESS_I225 0x00000004 /* Block SW access */ 1130 #define IGC_FWSM_FW_VALID_I225 0x8000 /* FW valid bit */ 1131 1132 #define IGC_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */ 1133 #define IGC_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 1134 #define IGC_NVM_RW_REG_START 1 /* Start operation */ 1135 #define IGC_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1136 #define IGC_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 1137 #define IGC_NVM_POLL_READ 0 /* Flag for polling for read complete */ 1138 #define IGC_FLASH_UPDATES 2000 1139 1140 /* NVM Word Offsets */ 1141 #define NVM_COMPAT 0x0003 1142 #define NVM_ID_LED_SETTINGS 0x0004 1143 #define NVM_VERSION 0x0005 1144 #define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */ 1145 #define NVM_PHY_CLASS_WORD 0x0007 1146 #define IGC_I210_NVM_FW_MODULE_PTR 0x0010 1147 #define IGC_I350_NVM_FW_MODULE_PTR 0x0051 1148 #define NVM_FUTURE_INIT_WORD1 0x0019 1149 #define NVM_ETRACK_WORD 0x0042 1150 #define NVM_ETRACK_HIWORD 0x0043 1151 #define NVM_COMB_VER_OFF 0x0083 1152 #define NVM_COMB_VER_PTR 0x003d 1153 1154 /* NVM version defines */ 1155 #define NVM_MAJOR_MASK 0xF000 1156 #define NVM_MINOR_MASK 0x0FF0 1157 #define NVM_IMAGE_ID_MASK 0x000F 1158 #define NVM_COMB_VER_MASK 0x00FF 1159 #define NVM_MAJOR_SHIFT 12 1160 #define NVM_MINOR_SHIFT 4 1161 #define NVM_COMB_VER_SHFT 8 1162 #define NVM_VER_INVALID 0xFFFF 1163 #define NVM_ETRACK_SHIFT 16 1164 #define NVM_ETRACK_VALID 0x8000 1165 #define NVM_NEW_DEC_MASK 0x0F00 1166 #define NVM_HEX_CONV 16 1167 #define NVM_HEX_TENS 10 1168 1169 /* FW version defines */ 1170 /* Offset of "Loader patch ptr" in Firmware Header */ 1171 #define IGC_I350_NVM_FW_LOADER_PATCH_PTR_OFFSET 0x01 1172 /* Patch generation hour & minutes */ 1173 #define IGC_I350_NVM_FW_VER_WORD1_OFFSET 0x04 1174 /* Patch generation month & day */ 1175 #define IGC_I350_NVM_FW_VER_WORD2_OFFSET 0x05 1176 /* Patch generation year */ 1177 #define IGC_I350_NVM_FW_VER_WORD3_OFFSET 0x06 1178 /* Patch major & minor numbers */ 1179 #define IGC_I350_NVM_FW_VER_WORD4_OFFSET 0x07 1180 1181 #define NVM_MAC_ADDR 0x0000 1182 #define NVM_SUB_DEV_ID 0x000B 1183 #define NVM_SUB_VEN_ID 0x000C 1184 #define NVM_DEV_ID 0x000D 1185 #define NVM_VEN_ID 0x000E 1186 #define NVM_INIT_CTRL_2 0x000F 1187 #define NVM_INIT_CTRL_4 0x0013 1188 #define NVM_LED_1_CFG 0x001C 1189 #define NVM_LED_0_2_CFG 0x001F 1190 1191 #define NVM_COMPAT_VALID_CSUM 0x0001 1192 #define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040 1193 1194 #define NVM_INIT_CONTROL2_REG 0x000F 1195 #define NVM_INIT_CONTROL3_PORT_B 0x0014 1196 #define NVM_INIT_3GIO_3 0x001A 1197 #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 1198 #define NVM_INIT_CONTROL3_PORT_A 0x0024 1199 #define NVM_CFG 0x0012 1200 #define NVM_ALT_MAC_ADDR_PTR 0x0037 1201 #define NVM_CHECKSUM_REG 0x003F 1202 #define NVM_COMPATIBILITY_REG_3 0x0003 1203 #define NVM_COMPATIBILITY_BIT_MASK 0x8000 1204 1205 #define IGC_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ 1206 #define IGC_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ 1207 #define IGC_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */ 1208 #define IGC_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */ 1209 1210 #define NVM_82580_LAN_FUNC_OFFSET(a) ( \ 1211 __extension__ ({ \ 1212 typeof(a) _a = (a); \ 1213 _a ? (0x40 + 0x40 * _a) : 0; \ 1214 })) 1215 1216 /* Mask bits for fields in Word 0x24 of the NVM */ 1217 #define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */ 1218 #define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed extrnl */ 1219 /* Offset of Link Mode bits for 82575/82576 */ 1220 #define NVM_WORD24_LNK_MODE_OFFSET 8 1221 /* Offset of Link Mode bits for 82580 up */ 1222 #define NVM_WORD24_82580_LNK_MODE_OFFSET 4 1223 1224 1225 /* Mask bits for fields in Word 0x0f of the NVM */ 1226 #define NVM_WORD0F_PAUSE_MASK 0x3000 1227 #define NVM_WORD0F_PAUSE 0x1000 1228 #define NVM_WORD0F_ASM_DIR 0x2000 1229 #define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 1230 1231 /* Mask bits for fields in Word 0x1a of the NVM */ 1232 #define NVM_WORD1A_ASPM_MASK 0x000C 1233 1234 /* Mask bits for fields in Word 0x03 of the EEPROM */ 1235 #define NVM_COMPAT_LOM 0x0800 1236 1237 /* length of string needed to store PBA number */ 1238 #define IGC_PBANUM_LENGTH 11 1239 1240 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 1241 #define NVM_SUM 0xBABA 1242 1243 /* PBA (printed board assembly) number words */ 1244 #define NVM_PBA_OFFSET_0 8 1245 #define NVM_PBA_OFFSET_1 9 1246 #define NVM_PBA_PTR_GUARD 0xFAFA 1247 #define NVM_RESERVED_WORD 0xFFFF 1248 #define NVM_PHY_CLASS_A 0x8000 1249 #define NVM_SERDES_AMPLITUDE_MASK 0x000F 1250 #define NVM_SIZE_MASK 0x1C00 1251 #define NVM_SIZE_SHIFT 10 1252 #define NVM_WORD_SIZE_BASE_SHIFT 6 1253 #define NVM_SWDPIO_EXT_SHIFT 4 1254 1255 /* NVM Commands - Microwire */ 1256 #define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */ 1257 #define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */ 1258 #define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */ 1259 #define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */ 1260 #define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erase/write disable */ 1261 1262 /* NVM Commands - SPI */ 1263 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 1264 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 1265 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 1266 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 1267 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 1268 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 1269 1270 /* SPI NVM Status Register */ 1271 #define NVM_STATUS_RDY_SPI 0x01 1272 1273 /* Word definitions for ID LED Settings */ 1274 #define ID_LED_RESERVED_0000 0x0000 1275 #define ID_LED_RESERVED_FFFF 0xFFFF 1276 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 1277 (ID_LED_OFF1_OFF2 << 8) | \ 1278 (ID_LED_DEF1_DEF2 << 4) | \ 1279 (ID_LED_DEF1_DEF2)) 1280 #define ID_LED_DEF1_DEF2 0x1 1281 #define ID_LED_DEF1_ON2 0x2 1282 #define ID_LED_DEF1_OFF2 0x3 1283 #define ID_LED_ON1_DEF2 0x4 1284 #define ID_LED_ON1_ON2 0x5 1285 #define ID_LED_ON1_OFF2 0x6 1286 #define ID_LED_OFF1_DEF2 0x7 1287 #define ID_LED_OFF1_ON2 0x8 1288 #define ID_LED_OFF1_OFF2 0x9 1289 1290 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 1291 #define IGP_ACTIVITY_LED_ENABLE 0x0300 1292 #define IGP_LED3_MODE 0x07000000 1293 1294 /* PCI/PCI-X/PCI-EX Config space */ 1295 #define PCIX_COMMAND_REGISTER 0xE6 1296 #define PCIX_STATUS_REGISTER_LO 0xE8 1297 #define PCIX_STATUS_REGISTER_HI 0xEA 1298 #define PCI_HEADER_TYPE_REGISTER 0x0E 1299 #define PCIE_LINK_STATUS 0x12 1300 #define PCIE_DEVICE_CONTROL2 0x28 1301 1302 #define PCIX_COMMAND_MMRBC_MASK 0x000C 1303 #define PCIX_COMMAND_MMRBC_SHIFT 0x2 1304 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060 1305 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 1306 #define PCIX_STATUS_HI_MMRBC_4K 0x3 1307 #define PCIX_STATUS_HI_MMRBC_2K 0x2 1308 #define PCIX_STATUS_LO_FUNC_MASK 0x7 1309 #define PCI_HEADER_TYPE_MULTIFUNC 0x80 1310 #define PCIE_LINK_WIDTH_MASK 0x3F0 1311 #define PCIE_LINK_WIDTH_SHIFT 4 1312 #define PCIE_LINK_SPEED_MASK 0x0F 1313 #define PCIE_LINK_SPEED_2500 0x01 1314 #define PCIE_LINK_SPEED_5000 0x02 1315 #define PCIE_DEVICE_CONTROL2_16ms 0x0005 1316 1317 #define ETH_ADDR_LEN 6 1318 1319 #define PHY_REVISION_MASK 0xFFFFFFF0 1320 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 1321 #define MAX_PHY_MULTI_PAGE_REG 0xF 1322 1323 /* Bit definitions for valid PHY IDs. 1324 * I = Integrated 1325 * E = External 1326 */ 1327 #define M88IGC_E_PHY_ID 0x01410C50 1328 #define M88IGC_I_PHY_ID 0x01410C30 1329 #define M88E1011_I_PHY_ID 0x01410C20 1330 #define IGP01IGC_I_PHY_ID 0x02A80380 1331 #define M88E1111_I_PHY_ID 0x01410CC0 1332 #define M88E1543_E_PHY_ID 0x01410EA0 1333 #define M88E1512_E_PHY_ID 0x01410DD0 1334 #define M88E1112_E_PHY_ID 0x01410C90 1335 #define I347AT4_E_PHY_ID 0x01410DC0 1336 #define M88E1340M_E_PHY_ID 0x01410DF0 1337 #define GG82563_E_PHY_ID 0x01410CA0 1338 #define IGP03IGC_E_PHY_ID 0x02A80390 1339 #define IFE_E_PHY_ID 0x02A80330 1340 #define IFE_PLUS_E_PHY_ID 0x02A80320 1341 #define IFE_C_E_PHY_ID 0x02A80310 1342 #define BMIGC_E_PHY_ID 0x01410CB0 1343 #define BMIGC_E_PHY_ID_R2 0x01410CB1 1344 #define I82577_E_PHY_ID 0x01540050 1345 #define I82578_E_PHY_ID 0x004DD040 1346 #define I82579_E_PHY_ID 0x01540090 1347 #define I217_E_PHY_ID 0x015400A0 1348 #define I82580_I_PHY_ID 0x015403A0 1349 #define I350_I_PHY_ID 0x015403B0 1350 #define I210_I_PHY_ID 0x01410C00 1351 #define IGP04IGC_E_PHY_ID 0x02A80391 1352 #define M88_VENDOR 0x0141 1353 #define I225_I_PHY_ID 0x67C9DC00 1354 1355 /* M88E1000 Specific Registers */ 1356 #define M88IGC_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */ 1357 #define M88IGC_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */ 1358 #define M88IGC_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Cntrl */ 1359 #define M88IGC_RX_ERR_CNTR 0x15 /* Receive Error Counter */ 1360 1361 #define M88IGC_PHY_EXT_CTRL 0x1A /* PHY extend control register */ 1362 #define M88IGC_PHY_PAGE_SELECT 0x1D /* Reg 29 for pg number setting */ 1363 #define M88IGC_PHY_GEN_CONTROL 0x1E /* meaning depends on reg 29 */ 1364 #define M88IGC_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ 1365 #define M88IGC_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ 1366 1367 /* M88E1000 PHY Specific Control Register */ 1368 #define M88IGC_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */ 1369 /* MDI Crossover Mode bits 6:5 Manual MDI configuration */ 1370 #define M88IGC_PSCR_MDI_MANUAL_MODE 0x0000 1371 #define M88IGC_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 1372 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 1373 #define M88IGC_PSCR_AUTO_X_1000T 0x0040 1374 /* Auto crossover enabled all speeds */ 1375 #define M88IGC_PSCR_AUTO_X_MODE 0x0060 1376 #define M88IGC_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */ 1377 1378 /* M88E1000 PHY Specific Status Register */ 1379 #define M88IGC_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 1380 #define M88IGC_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 1381 #define M88IGC_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 1382 /* 0 = <50M 1383 * 1 = 50-80M 1384 * 2 = 80-110M 1385 * 3 = 110-140M 1386 * 4 = >140M 1387 */ 1388 #define M88IGC_PSSR_CABLE_LENGTH 0x0380 1389 #define M88IGC_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ 1390 #define M88IGC_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 1391 #define M88IGC_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 1392 #define M88IGC_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 1393 #define M88IGC_PSSR_100MBS 0x4000 /* 01=100Mbs */ 1394 #define M88IGC_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 1395 1396 #define M88IGC_PSSR_CABLE_LENGTH_SHIFT 7 1397 1398 /* Number of times we will attempt to autonegotiate before downshifting if we 1399 * are the master 1400 */ 1401 #define M88IGC_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 1402 #define M88IGC_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 1403 /* Number of times we will attempt to autonegotiate before downshifting if we 1404 * are the slave 1405 */ 1406 #define M88IGC_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 1407 #define M88IGC_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 1408 #define M88IGC_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 1409 1410 /* Intel I347AT4 Registers */ 1411 #define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */ 1412 #define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */ 1413 #define I347AT4_PAGE_SELECT 0x16 1414 1415 /* I347AT4 Extended PHY Specific Control Register */ 1416 1417 /* Number of times we will attempt to autonegotiate before downshifting if we 1418 * are the master 1419 */ 1420 #define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800 1421 #define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000 1422 #define I347AT4_PSCR_DOWNSHIFT_1X 0x0000 1423 #define I347AT4_PSCR_DOWNSHIFT_2X 0x1000 1424 #define I347AT4_PSCR_DOWNSHIFT_3X 0x2000 1425 #define I347AT4_PSCR_DOWNSHIFT_4X 0x3000 1426 #define I347AT4_PSCR_DOWNSHIFT_5X 0x4000 1427 #define I347AT4_PSCR_DOWNSHIFT_6X 0x5000 1428 #define I347AT4_PSCR_DOWNSHIFT_7X 0x6000 1429 #define I347AT4_PSCR_DOWNSHIFT_8X 0x7000 1430 1431 /* I347AT4 PHY Cable Diagnostics Control */ 1432 #define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */ 1433 1434 /* M88E1112 only registers */ 1435 #define M88E1112_VCT_DSP_DISTANCE 0x001A 1436 1437 /* M88EC018 Rev 2 specific DownShift settings */ 1438 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 1439 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 1440 1441 #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 1442 #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C 1443 1444 /* BME1000 PHY Specific Control Register */ 1445 #define BMIGC_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ 1446 1447 /* Bits... 1448 * 15-5: page 1449 * 4-0: register offset 1450 */ 1451 #define GG82563_PAGE_SHIFT 5 1452 #define GG82563_REG(page, reg) \ 1453 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 1454 #define GG82563_MIN_ALT_REG 30 1455 1456 /* GG82563 Specific Registers */ 1457 #define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */ 1458 #define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */ 1459 #define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */ 1460 #define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */ 1461 1462 /* MAC Specific Control Register */ 1463 #define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21) 1464 1465 #define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */ 1466 1467 /* Page 193 - Port Control Registers */ 1468 /* Kumeran Mode Control */ 1469 #define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16) 1470 #define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Pwr Mgt Ctrl */ 1471 1472 /* Page 194 - KMRN Registers */ 1473 #define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) /* Inband Ctrl */ 1474 1475 /* MDI Control */ 1476 #define IGC_MDIC_DATA_MASK 0x0000FFFF 1477 #define IGC_MDIC_INT_EN 0x20000000 1478 #define IGC_MDIC_REG_MASK 0x001F0000 1479 #define IGC_MDIC_REG_SHIFT 16 1480 #define IGC_MDIC_PHY_MASK 0x03E00000 1481 #define IGC_MDIC_PHY_SHIFT 21 1482 #define IGC_MDIC_OP_WRITE 0x04000000 1483 #define IGC_MDIC_OP_READ 0x08000000 1484 #define IGC_MDIC_READY 0x10000000 1485 #define IGC_MDIC_ERROR 0x40000000 1486 #define IGC_MDIC_DEST 0x80000000 1487 1488 #define IGC_N0_QUEUE -1 1489 1490 #define IGC_MAX_MAC_HDR_LEN 127 1491 #define IGC_MAX_NETWORK_HDR_LEN 511 1492 1493 #define IGC_VLAPQF_QUEUE_SEL(_n, q_idx) ((q_idx) << ((_n) * 4)) 1494 #define IGC_VLAPQF_P_VALID(_n) (0x1 << (3 + (_n) * 4)) 1495 #define IGC_VLAPQF_QUEUE_MASK 0x03 1496 #define IGC_VFTA_BLOCK_SIZE 8 1497 /* SerDes Control */ 1498 #define IGC_GEN_CTL_READY 0x80000000 1499 #define IGC_GEN_CTL_ADDRESS_SHIFT 8 1500 #define IGC_GEN_POLL_TIMEOUT 640 1501 1502 /* LinkSec register fields */ 1503 #define IGC_LSECTXCAP_SUM_MASK 0x00FF0000 1504 #define IGC_LSECTXCAP_SUM_SHIFT 16 1505 #define IGC_LSECRXCAP_SUM_MASK 0x00FF0000 1506 #define IGC_LSECRXCAP_SUM_SHIFT 16 1507 1508 #define IGC_LSECTXCTRL_EN_MASK 0x00000003 1509 #define IGC_LSECTXCTRL_DISABLE 0x0 1510 #define IGC_LSECTXCTRL_AUTH 0x1 1511 #define IGC_LSECTXCTRL_AUTH_ENCRYPT 0x2 1512 #define IGC_LSECTXCTRL_AISCI 0x00000020 1513 #define IGC_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 1514 #define IGC_LSECTXCTRL_RSV_MASK 0x000000D8 1515 1516 #define IGC_LSECRXCTRL_EN_MASK 0x0000000C 1517 #define IGC_LSECRXCTRL_EN_SHIFT 2 1518 #define IGC_LSECRXCTRL_DISABLE 0x0 1519 #define IGC_LSECRXCTRL_CHECK 0x1 1520 #define IGC_LSECRXCTRL_STRICT 0x2 1521 #define IGC_LSECRXCTRL_DROP 0x3 1522 #define IGC_LSECRXCTRL_PLSH 0x00000040 1523 #define IGC_LSECRXCTRL_RP 0x00000080 1524 #define IGC_LSECRXCTRL_RSV_MASK 0xFFFFFF33 1525 1526 /* Tx Rate-Scheduler Config fields */ 1527 #define IGC_RTTBCNRC_RS_ENA 0x80000000 1528 #define IGC_RTTBCNRC_RF_DEC_MASK 0x00003FFF 1529 #define IGC_RTTBCNRC_RF_INT_SHIFT 14 1530 #define IGC_RTTBCNRC_RF_INT_MASK \ 1531 (IGC_RTTBCNRC_RF_DEC_MASK << IGC_RTTBCNRC_RF_INT_SHIFT) 1532 1533 /* DMA Coalescing register fields */ 1534 /* DMA Coalescing Watchdog Timer */ 1535 #define IGC_DMACR_DMACWT_MASK 0x00003FFF 1536 /* DMA Coalescing Rx Threshold */ 1537 #define IGC_DMACR_DMACTHR_MASK 0x00FF0000 1538 #define IGC_DMACR_DMACTHR_SHIFT 16 1539 /* Lx when no PCIe transactions */ 1540 #define IGC_DMACR_DMAC_LX_MASK 0x30000000 1541 #define IGC_DMACR_DMAC_LX_SHIFT 28 1542 #define IGC_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ 1543 /* DMA Coalescing BMC-to-OS Watchdog Enable */ 1544 #define IGC_DMACR_DC_BMC2OSW_EN 0x00008000 1545 1546 /* DMA Coalescing Transmit Threshold */ 1547 #define IGC_DMCTXTH_DMCTTHR_MASK 0x00000FFF 1548 1549 #define IGC_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */ 1550 1551 /* Rx Traffic Rate Threshold */ 1552 #define IGC_DMCRTRH_UTRESH_MASK 0x0007FFFF 1553 /* Rx packet rate in current window */ 1554 #define IGC_DMCRTRH_LRPRCW 0x80000000 1555 1556 /* DMA Coal Rx Traffic Current Count */ 1557 #define IGC_DMCCNT_CCOUNT_MASK 0x01FFFFFF 1558 1559 /* Flow ctrl Rx Threshold High val */ 1560 #define IGC_FCRTC_RTH_COAL_MASK 0x0003FFF0 1561 #define IGC_FCRTC_RTH_COAL_SHIFT 4 1562 /* Lx power decision based on DMA coal */ 1563 #define IGC_PCIEMISC_LX_DECISION 0x00000080 1564 1565 #define IGC_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */ 1566 #define IGC_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */ 1567 #define IGC_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */ 1568 #define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */ 1569 #define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ 1570 1571 1572 #define I225_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */ 1573 #define I225_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ 1574 #define IGC_RXPBS_SIZE_I225_MASK 0x0000003F /* Rx packet buffer size */ 1575 #define IGC_TXPB0S_SIZE_I225_MASK 0x0000003F /* Tx packet buffer 0 size */ 1576 #define IGC_STM_OPCODE 0xDB00 1577 #define IGC_EEPROM_FLASH_SIZE_WORD 0x11 1578 #define INVM_DWORD_TO_RECORD_TYPE(invm_dword) \ 1579 (u8)((invm_dword) & 0x7) 1580 #define INVM_DWORD_TO_WORD_ADDRESS(invm_dword) \ 1581 (u8)(((invm_dword) & 0x0000FE00) >> 9) 1582 #define INVM_DWORD_TO_WORD_DATA(invm_dword) \ 1583 (u16)(((invm_dword) & 0xFFFF0000) >> 16) 1584 #define IGC_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS 8 1585 #define IGC_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS 1 1586 #define IGC_INVM_ULT_BYTES_SIZE 8 1587 #define IGC_INVM_RECORD_SIZE_IN_BYTES 4 1588 #define IGC_INVM_VER_FIELD_ONE 0x1FF8 1589 #define IGC_INVM_VER_FIELD_TWO 0x7FE000 1590 #define IGC_INVM_IMGTYPE_FIELD 0x1F800000 1591 1592 #define IGC_INVM_MAJOR_MASK 0x3F0 1593 #define IGC_INVM_MINOR_MASK 0xF 1594 #define IGC_INVM_MAJOR_SHIFT 4 1595 1596 /* PLL Defines */ 1597 #define IGC_PCI_PMCSR 0x44 1598 #define IGC_PCI_PMCSR_D3 0x03 1599 #define IGC_MAX_PLL_TRIES 5 1600 #define IGC_PHY_PLL_UNCONF 0xFF 1601 #define IGC_PHY_PLL_FREQ_PAGE 0xFC0000 1602 #define IGC_PHY_PLL_FREQ_REG 0x000E 1603 #define IGC_INVM_DEFAULT_AL 0x202F 1604 #define IGC_INVM_AUTOLOAD 0x0A 1605 #define IGC_INVM_PLL_WO_VAL 0x0010 1606 1607 /* Proxy Filter Control Extended */ 1608 #define IGC_PROXYFCEX_MDNS 0x00000001 /* mDNS */ 1609 #define IGC_PROXYFCEX_MDNS_M 0x00000002 /* mDNS Multicast */ 1610 #define IGC_PROXYFCEX_MDNS_U 0x00000004 /* mDNS Unicast */ 1611 #define IGC_PROXYFCEX_IPV4_M 0x00000008 /* IPv4 Multicast */ 1612 #define IGC_PROXYFCEX_IPV6_M 0x00000010 /* IPv6 Multicast */ 1613 #define IGC_PROXYFCEX_IGMP 0x00000020 /* IGMP */ 1614 #define IGC_PROXYFCEX_IGMP_M 0x00000040 /* IGMP Multicast */ 1615 #define IGC_PROXYFCEX_ARPRES 0x00000080 /* ARP Response */ 1616 #define IGC_PROXYFCEX_ARPRES_D 0x00000100 /* ARP Response Directed */ 1617 #define IGC_PROXYFCEX_ICMPV4 0x00000200 /* ICMPv4 */ 1618 #define IGC_PROXYFCEX_ICMPV4_D 0x00000400 /* ICMPv4 Directed */ 1619 #define IGC_PROXYFCEX_ICMPV6 0x00000800 /* ICMPv6 */ 1620 #define IGC_PROXYFCEX_ICMPV6_D 0x00001000 /* ICMPv6 Directed */ 1621 #define IGC_PROXYFCEX_DNS 0x00002000 /* DNS */ 1622 1623 /* Proxy Filter Control */ 1624 #define IGC_PROXYFC_D0 0x00000001 /* Enable offload in D0 */ 1625 #define IGC_PROXYFC_EX 0x00000004 /* Directed exact proxy */ 1626 #define IGC_PROXYFC_MC 0x00000008 /* Directed MC Proxy */ 1627 #define IGC_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */ 1628 #define IGC_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */ 1629 #define IGC_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */ 1630 #define IGC_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */ 1631 #define IGC_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */ 1632 #define IGC_PROXYFC_NS_DIRECTED 0x00000400 /* Directed NS Proxy Ena */ 1633 #define IGC_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Ena */ 1634 /* Proxy Status */ 1635 #define IGC_PROXYS_CLEAR 0xFFFFFFFF /* Clear */ 1636 1637 /* Firmware Status */ 1638 #define IGC_FWSTS_FWRI 0x80000000 /* FW Reset Indication */ 1639 /* VF Control */ 1640 #define IGC_VTCTRL_RST 0x04000000 /* Reset VF */ 1641 1642 #define IGC_STATUS_LAN_ID_MASK 0x00000000C /* Mask for Lan ID field */ 1643 /* Lan ID bit field offset in status register */ 1644 #define IGC_STATUS_LAN_ID_OFFSET 2 1645 #define IGC_VFTA_ENTRIES 128 1646 1647 #define IGC_UNUSEDARG 1648 #define ERROR_REPORT(fmt) do { } while (0) 1649 #endif /* _IGC_DEFINES_H_ */ 1650